AFE7681

활성

4전송, 2수신 RF 샘플링 트랜시버, 100MHz~5.2GHz, 최대 1200MHz IBW

제품 상세 정보

Applications Wireless infrastructure Number of TXs and RXs 4 TX, 2 RX RF frequency (max) (MHz) 5200 RF frequency (min) (MHz) 100 Number of DUCs per TX 1 Number of DDCs per RX 1 Operating temperature range (°C) -40 to 85 Rating Catalog
Applications Wireless infrastructure Number of TXs and RXs 4 TX, 2 RX RF frequency (max) (MHz) 5200 RF frequency (min) (MHz) 100 Number of DUCs per TX 1 Number of DDCs per RX 1 Operating temperature range (°C) -40 to 85 Rating Catalog
FCBGA (ABJ) 400 289 mm² 17 x 17
  • 14-Bit resolution
  • Sample rate:
    • DAC: 9GSPS
    • ADC: 3GSPS
  • RF Frequency range: up to 5.2 GHz
  • Maximum RF signal bandwidth
    • Quad-channel mode (4T4R): 800 MHz (single-band); 300 MHz (dual-band)
    • Dual-channel mode (2T2R): 1200 MHz (TX)/1000 MHz (RX) (single-band); 800MHz(dual-band)
  • On-chip dual selectable DSAs per RX channel
  • Integrated TX DSA functionality
  • Digital:
    • Dual band digital up-converters (DUCs)
    • Dual Band digital down-converters (DDCs)
    • 32-Bit NCOs for DUCs/DDCs
    • Interpolation ratio: 6x, 8x, 9x, 12x, 16x, 18x, 24x, 36x
    • Decimation ratio: /2, /3, /4, /6, /8, /9, /12, /16, /18, /24, /32
    • RX/FB Dynamic switching for TDD
  • Interface:
    • 8 SerDes Transceivers up to 15Gbps
    • 16-Bit and 12-bit JESD204B transport layer formatting with 8b/10b encoding
    • Subclass 1 multi-device synchronization
  • Clock:
    • Internal PLL/VCO to generate DAC and ADC clocks
  • Package: 17mm x 17mm FC BGA, 0.8mm pitch
  • Power supplies: 1.85 V, 1.15 V, 1.0 V, –1.8 V
  • 14-Bit resolution
  • Sample rate:
    • DAC: 9GSPS
    • ADC: 3GSPS
  • RF Frequency range: up to 5.2 GHz
  • Maximum RF signal bandwidth
    • Quad-channel mode (4T4R): 800 MHz (single-band); 300 MHz (dual-band)
    • Dual-channel mode (2T2R): 1200 MHz (TX)/1000 MHz (RX) (single-band); 800MHz(dual-band)
  • On-chip dual selectable DSAs per RX channel
  • Integrated TX DSA functionality
  • Digital:
    • Dual band digital up-converters (DUCs)
    • Dual Band digital down-converters (DDCs)
    • 32-Bit NCOs for DUCs/DDCs
    • Interpolation ratio: 6x, 8x, 9x, 12x, 16x, 18x, 24x, 36x
    • Decimation ratio: /2, /3, /4, /6, /8, /9, /12, /16, /18, /24, /32
    • RX/FB Dynamic switching for TDD
  • Interface:
    • 8 SerDes Transceivers up to 15Gbps
    • 16-Bit and 12-bit JESD204B transport layer formatting with 8b/10b encoding
    • Subclass 1 multi-device synchronization
  • Clock:
    • Internal PLL/VCO to generate DAC and ADC clocks
  • Package: 17mm x 17mm FC BGA, 0.8mm pitch
  • Power supplies: 1.85 V, 1.15 V, 1.0 V, –1.8 V

The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.

The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.

The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.

The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.

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추가 정보 요청

상용 무선 전용 AFE7681에 대한 전체 데이터 시트 및 기타 설계 리소스를 참조하십시오. 지금 요청

다른 모든 애플리케이션의 경우 TI의 범용 RF 샘플링 AFE를 참조하십시오.

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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3개 모두 보기
상위 문서 유형 직함 형식 옵션 날짜
* Data sheet AFE76xx Quad/dual-channel, RF sampling analog front-end with 14-bit 9GSPS DACs and 14-bit 3GSPS ADCs datasheet (Rev. E) PDF | HTML 2019/03/01
Application note Temp Profile to Maintain Optimum FIT Performance 2019/07/23
Application note RF Sampling for Multi-band Radios 2018/11/26

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

드라이버 또는 라이브러리

AFE768X-DESIGN AFE768x Design Files

Design resources for AFE768x Transceivers
지원되는 제품 및 하드웨어

지원되는 제품 및 하드웨어

펌웨어

TI204C-IP Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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평가 모듈(EVM)용 GUI

DATACONVERTERPRO-SW High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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지원되는 제품 및 하드웨어

패키지 CAD 기호, 풋프린트 및 3D 모델
FCBGA (ABJ) 400 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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