ZHCSL05C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. 器件功能方框图
  6. Revision History
  7. 说明(续)
  8. Device Option Table
  9. Pin Configuration and Functions
  10. Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Analog Wake-up and Failure Latch

The analog wake-up detection circuit monitors the WAKE pin when the device is in the OFF state. With a valid power supply at the supply input pins (VIN, AVIN, and VIN_SAFE), this circuit is the only active circuit in the device when the device is in the OFF state, reducing device power consumption.

When the WAKE pin is driven high, the device deglitches the input wake-up signal using a low-power oscillator clock for approximately 130 µs and latches the signal in the analog wake-up latch (indicated as a WAKE_L bit). When the WAKE_L bit is set, the wake-up latch is cleared only by the device NPOR event, a SPI command (CLR_WAKE_LATCH), or failure conditions that force the device to go to the OFF state (fault events 2 through 17). The wake-up latch is also cleared anytime when the device goes into the OFF state.

The wake-up latch is cleared as the device starts to go to the OFF state. The internal signal that clears the wake-up latch remains active (keep clearing the power wake-up latch) until the device goes to the OFF state. This prevents the wake-up latch from getting set again and triggers a new power-up before the device goes into the OFF state.

In addition to the power wake-up latch, the analog wake-up latch includes additional analog latches (Analog_Latch) to retain failure conditions that force the device to go to the OFF state. The list of latches includes the following:

  1. NPOR latch
  2. Analog or digital system-clock-monitor failure latch
  3. RESET state time-out latch
  4. EEPROM CRC failure latch
  5. BUCK1 overtemperature latch
  6. BUCK1 short-circuit-to-ground latch
  7. BUCK1 overvoltage protection latch
  8. BUCK1 low-side sink overcurrent latch
  9. BUCK1 extreme overvoltage protection latch
  10. BUCK1 power ground loss latch
  11. BUCK2 overvoltage protection latch
    Note:

    In case the BUCK2 overvoltage condition is still detected 28 µs to 30 µs after the BUCK2 regulator is disabled, the device goes to the OFF state and the BUCK2_OVP status bit is latched in the Analog_Latch.

  12. BOOST overvoltage protection latch
    Note:

    In case the BOOST overvoltage condition is still detected 72 µs to 80 µs after the BOOST converter is disabled, the device goes to the OFF state and the BOOST OVP status bit is latched in the Analog_Latch.

  13. VREG undervoltage latch
  14. VREG overvoltage latch
  15. VIN overvoltage latch
  16. Device error-counter power-down latch
  17. Start-up time-out latch

These status latches are set in the analog power domain of the TPS65313-Q1 device as the device goes into the OFF state. These latches are cleared only if the device loses battery supply at the AVIN pin or when the device wakes up and exits the OFF state after a valid WAKE input event. As the device starts up after a valid WAKE input event, the content of the analog status latches are copied to the OFF_STATE_L_STAT and the corresponding BUCK1, VMON, and SAFETY status registers after an internal NPOR is asserted high and the EEPROM has been downloaded. Then the analog status latches are cleared.

Table 11-14 OFF-State Conditions and Corresponding Status Bits
NUMBER OFF STATE CONDITION OFF_STATE_L REGISTER BIT CORRESPONDING STATUS REGISTER BIT
1. Power-on reset POWER_ON_RST
2. Analog or digital system clock-monitor error SYSCLK_ERR ANA_SYSCLK_ERR bit and DIG_SYSCLK_ERR bit in SAFETY_CLK_STAT register
3. RESET state time-out RESET_TO
4. EEPROM CRC error EE_CRC_ERR EE_CRC_ERR bit in SAFETY_ERR_STAT1 register
5. BUCK1 overtemperature BUCKx_BOOST_VREG_FAIL BUCK1_OT_STD bit in SAFETY_BUCK1_STAT1 register
6. BUCK1 short-circuit to GND BUCKx_BOOST_VREG_FAIL BUCK1_SCG bit in SAFETY_BUCK1_STAT1 register
7. BUCK1 overvoltage protection BUCKx_BOOST_VREG_FAIL BUCK1_OVP bit in SAFETY_BUCK1_STAT1 register
8. BUCK1 low-side sink overcurrent BUCKx_BOOST_VREG_FAIL BUCK1_LS_SINK_OVC bit in SAFETY_BUCK1_STAT1 register
9. BUCK1 extreme overvoltage protection BUCKx_BOOST_VREG_FAIL BUCK1_EOVP bit in SAFETY_BUCK1_STAT1 register
10. BUCK1 power GND loss BUCKx_BOOST_VREG_FAIL BUCK1_PGND_LOSS bit in SAFETY_BUCK1_STAT1 register
11. BUCK2 overvoltage protection BUCKx_BOOST_VREG_FAIL BUCK2_OVP bit in SAFETY_BUCK2_STAT1 register
12. BOOST overvoltage protection BUCKx_BOOST_VREG_FAIL BOOST_OVP bit in SAFETY_BOOST_STAT1 register
13. VREG undervoltage BUCKx_BOOST_VREG_FAIL VREG_UV bit in VMON_UV_STAT register
14. VREG overvoltage BUCKx_BOOST_VREG_FAIL VREG_OV bit in VMON_OV_STAT register
15. VIN overvoltage VIN_OV VIN_OV bit in VMON_OV_STAT register
16. Device error-counter power down DEV_EC_PDWN
17. Start-up time-out START_UP_TO

If a power-up time-out failure that puts the device in the OFF state is followed by a new power-up event (because the WAKE pin is driven above its VWAKE-ON threshold level), the number of analog-latched bits could be more than the START_UP_TO bit. The reason for this increased number of latched bits is because the previous OFF state transition condition could be caused by any of the previously listed OFF-state failure conditions.

The AUTO_START_DIS configuration bit is latched in the analog wake-up latch as well as in the DEV_STAT1 register. This bit is initialized to 0b at a NPOR event, only when an NPOR event is preceded by loss of battery supply at the VIN, VINA, and VIN_SAFE pins. The AUTO_START_DIS bit can be set to 1b by the SET_AUTO_START_DIS command with data 0xAA, or when a valid VREG OV event is detected. This bit can be cleared by the CLR_AUTO_START_DIS command with data 0x55. This bit controls whether the device's auto-restart is allowed, when the device goes to the OFF state, and while the WAKE input pin is still driven above its VWAKE-ON threshold level.

When the device is in the INIT state during power-up, the device NPOR stays asserted if the system-clock error, VIN overvoltage, or both are detected. The NPOR is asserted until the INIT state time-out event puts the device to the OFF state, and the START_UP_TO bit is latched in the Analog_Latch (the SYSCLK_ERR and VIN_OV bits are not latched in the Analog_Latch).

When the device starts and the NPOR for the digital core is released, the device goes into the OFF state with respective status bits latched in the Analog_Latch, if the SYSCLK failure, VIN supply overvoltage, or both are detected.