Layout is a very important part of good power-supply design. Several signal paths conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. Layout Example shows the PCB layout example. Obtaining acceptable performance with alternate PCB layouts may be possible.

In Layout Example, layout was optimized with the guidelines that follow:

• Provide a low-inductance, low-impedance supply and ground path which are critical. Route the input supply line (VIN plane) with a wide trace to minimize the trace impedance.
• Place the VIN input filter capacitors (C5, C6, and C19) very close to the device. Place the high frequency capacitor (C19) as close to the device pin as possible. A large PGND plane minimizes the parasitics of the input capacitor ground connection. A solid PGND ground plane on the second layer further minimizes the PGND plane impedance.
• Place the AVIN pin filter capacitor (C1) very close to the pin with a short connection to the AGND pin.
• Place the BUCK1 output capacitors (C8 and C9) close to the input capacitors and device PGND pin. Connect these capacitors with a large ground plane through multiple vias to reduce the switching loop impedance.
• Route the PH1 signal in an inner layer to minimize the emission from the switching plane. Use multiple vias to minimize the impedance of the PH1 power path.
• Route the BUCK2 input supply line (VSUP2) with a wide trace to minimize the trace impedance.
• Place the VSUP2 input filter capacitors (C10 and C20) very close to the device. Place the high frequency capacitor (C20) as close to the device pin as possible. A large PGND plane minimizes the parasitics of the input capacitor ground connection.
• Place the BUCK2 output capacitors (C12 and C13) close to the input capacitors and device PGND pin. Connect these capacitors with a large ground plane through multiple vias to decrease the switching loop impedance.
• Route the PH2 signal in an inner layer to minimize the emission from the switching plane. Use multiple vias to minimize the impedance of the PH2 power path.
• Route the BOOST supply line with a wide trace to minimize the trace impedance.
• Place the BOOST input capacitors (C14 and C21) and output capacitors (C6 and C17) very close to each other with short ground connections to minimize loop impedance.
• Route the PGND3 connection with a wide trace and multiple vias to minimize the impedance between the ground of the BOOST input and BOOST output capacitors and the device PGND3 pin.
• Route the PH3 signal with minimal loop area to minimize the emission from the switching plane. Use a wide trace to minimize the impedance for the PH3 power path.
• Place the VREG pin capacitor (C4) as close as possible to the VREG pin. Connect the ground pad of the capacitor to a solid ground plane to minimize the loop impedance.
• Connect all PBKGx, AGND,DGND, and PGNDx pins together at the device thermal pad to make a star connection below the device thermal pad.
• Connect the device thermal pad to the solid ground plane through multiple thermal vias to improve the thermal conductivity.
• Place the BOOT1, BOOT2, and BOOT3 capacitors on the bottom layer with two vias on each pin to minimize the parasitic impedance in the BOOTx path.
• Route the VSENSEx signals away from the switching node with minimum interaction with any noise sources associated with the switching components.