ZHCSL05C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 器件功能方框图
  6. 5 Revision History
  7. 6 说明（续）
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
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订购信息

11.9.10.2 WD Failure Counter and WD Status

The WD function uses a WD failure counter (WD_FAIL_CNT[3:0]) to track correct and incorrect MCU answers. The WD_FAIL_CNT[3:0] counter increments for each incorrect answer and decrements for each correct answer.

The WD_FAIL_CNT[3:0] counter is updated by the following events when the device is in the DIAGNOSTIC or ACTIVE or SAFE state:

  • A correct WD answer decrements the WD_FAIL_CNT[3:0] counter by 1.
  • A wrong WD answer increments the WD_FAIL_CNT[3:0] counter by 1.
  • An incomplete or missing WD answer for the duration of the programmed WD sequence duration (or WD time-out event) increments the WD_FAIL_CNT[3:0] counter by 1 and sets the TIME_OUT status bit in the WDT_STATUS register.
  • Any change in the WD_CFG bit, WD window time durations (WDT_WIN1_CFG or WDT_WIN2_CFG register), or WD answer generation configurations (WDT_QA_CFG register) increments the WD_FAIL_CNT[3:0] counter by 1.

When the value of the WD_FAIL_CNT[3:0] counter is less than the value set by the WD_FC_ENDRV_TH[3:0] bits, the WD function is considered to be in range, and the device keeps the WD-enabled function active (the ENDRV/nIRQ driver can be activated and the ENDRV/nIRQ pin is pulled high). The WD-enabled function is enabled by setting the ENDRV_EN control bit in the SAFETY_CHECK_CTRL register. When the value of the WD_FAIL_CNT[3:0] counter is greater than the value set by the WD_FC_ENDRV_TH[3:0] bits in the SAFETY_CFG4 register, the WD function is considered to be out of range, and the device disables the WD-enabled ENDRV/nIRQ function by driving ENDRV/nIRQ pin low. Figure 11-15 summarizes the settings of the WD status bits depending on the WD_FAIL_CNT[3:0] counter value with respect to the WD_FC_ENDRV_TH[3:0] bits value.

GUID-D7832C21-0362-41DA-87BA-96FFDCC74C55-low.gif
  1. When the condition is met, the device goes from the ACTIVE or DIAGNOSTIC state to the SAFE state. No action occurs if the device is in the SAFE state.
  2. When the condition is met, the device stays in the ACTIVE state if the MCU_ESM_RST_EN bit is 0b. When the condition is met, the device goes from the ACTIVE or DIAGNOSTIC state to the RESET state if the MCU_ESM_RST_EN bit is 1b
  3. When the condition is met, the device does not go from the ACTIVE or DIAGNOSTIC state to the SAFE state.
  4. When the condition is met, the device goes from the ACTIVE or DIAGNOSTIC state to the SAFE state.
Figure 11-15 Watchdog Impact on ENDRV/nIRQ Output Function
Table 11-8 WD Fail Counter Ranges for ENDRV Function
WD STATUS BITS WD_FAIL_CNT[3:0] = 0b 0b < WD_FAIL_CNT[3:0] < WD_FC_ENDRV_TH[3:0](2) WD_FAIL_CNT[3:0] ≥ WD_FC_ENDRV_TH[3:0](3)
WD_FAIL(1) 0b 1b 1b
WD_ENDRV_FAIL 0b 0b 1b
(1) The WD_FAIL status bit is set each time the WD_FAIL_CNT[3:0] counter increments.
(2) The WD is in range.
(3) The WD is out of range.

If the WD_RST_EN configuration bit in the SAFETY_CFG3 register is set to 1b, the WD generates a reset to the MCU by driving NRES pin low when the WD_FAIL_CNT[3:0] counter reaches the programmed threshold set by the WD_FC_RST_TH[3:0] bits. Table 11-9 summarizes the WD status bits and device state depending on the WD_FAIL_CNT[3:0] counter value with respect to WD_FC_RST_TH[3:0] bits value.

Table 11-9 WD Fail Counter Ranges for WD Reset
WD STATUS BITS WD_FAIL_CNT[3:0] = 0b 0b < WD_FAIL_CNT[3:0] < WD_FC_RST_TH[3:0](2) WD_FAIL_CNT[3:0] = WD_FC_RST_TH[3:0] and WD_RST_EN = 1b(3) WD_FAIL_CNT[3:0] = WD_FC_RST_TH[3:0] and WD_RST_EN = 0b(3)
WD_FAIL(1) 0b 1b 1b 1b
WD_RST_FAIL 0b 0b 1b 1b
Device State No change No change RESET state (4) SAFE state
(1) The WD_FAIL status bit is set each time the WD_FAIL_CNT[3:0] increments.
(2) The WD is in range.
(3) The WD is out of range.
(4) When device was in DIAGNOSTIC or ACTIVE state, or device was in SAFE state and SAFE_EXIT SPI command is received.

When a NPOR event occurs, the WD_FAIL_CNT[3:0] counter is initialized to 0x05, which is the initial value of the WD_FC_ENDRV_TH[3:0] bits. While the device is in the DIAGNOSTIC state, the MCU can set the desired WD_FC_ENDRV_TH[3:0] and WD_FC_RST_TH[3:0] values. Setting new WD_FC_ENDRV_TH[3:0] value in DIAGNOSTIC state causes the WD_FAIL_CNT[3:0] counter to be set to the same new value. This WD_FAIL_CNT[3:0] bits update is to make sure that the ENDRV function is initially disabled until correct WD answers are provided by the MCU.

When the WD_FAIL_CNT[3:0] counter reaches a count of 0xF, any new incorrect answer from the MCU does not change the counter value. The counter stays at 0xF. Similarly, when the WD_FAIL_CNT[3:0] counter reaches a count of 0x0, any new correct WD answers do not change the counter value. The counter stays at 0x0.