ZHCSL05C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. 器件功能方框图
  6. Revision History
  7. 说明(续)
  8. Device Option Table
  9. Pin Configuration and Functions
  10. Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  15. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Overcurrent Protection (Monitoring and Protection)

Currents through both the high-side (HS) power MOSFET and the low-side (LS) power MOSFET are continuously monitored to protect the internal power MOSFETs from damage. Current through each MOSFET is compared against two threshold levels (IHS/LS_SCG_ILIM_BUCK1 and IHS/LS_OVC_LIM_BUCK1). The former is to detect a short-circuit event and the latter is to detect an overload condition where the BUCK1 regulator is loaded with a current higher than what is specified.

If either the HS MOSFET current or the LS MOSFET current exceeds their respective overload current limits (IHS_OVC_ILIM_BUCK1 and ILS_OVC_ILIM_BUCK1) an overload event is detected and the BUCK1_OVC status bit is set in the SAFETY_BUCK1_STAT1 register; however, the regulator does not shut down. As the external inductor current continues to increase, and if either the HS MOSFET current or the LS MOSFET current exceeds their respective short-circuit current limit (IHS_SCG_ILIM_BUCK1 and ILS_SCG_ILIM_BUCK1), then the HS MOSFET is turned off immediately and the LS MOSFET is turned on, until the inductor current decreases to less than the overload threshold (ILS_OVC_ILIM_BUCK1). The BUCK1 regulator is then disabled and the BUCK1_SCG status bit is set in the SAFETY_BUCK1_STAT1 register. This double-sampling scheme allows for any overcurrent event to be detected either through a HS or LS MOSFET, especially when the BUCK1 regulator operates at a low duty cycle with a high input supply voltage. The BUCK1_SCG_OFF_EN configuration bit setting selects the device response after a short-circuit detection.

If the BUCK1_SCG_OFF_EN bit is set to 1b, the following occurs:

  • The BUCK1 regulator, BUCK2 regulator, and BOOST converter are disabled, while enabling discharge through the internal resistor.
  • The device goes into the OFF state.
  • The BUCK1_SCG status bit is latched in the Analog_Latch (to preserve it) while the device is in the OFF state and presented to the system MCU during the next power-up event from the OFF state.

If the BUCK1_SCG_OFF_EN bit is set to 0b, the following occurs:

  • The BUCK1 regulator, BUCK2 regulator, and BOOST converter are disabled, while disabling discharge through the internal resistor.
  • The device goes into the SAFE state.
    • Eventually, as the BUCK1 regulator, BUCK2 regulator, and BOOST converter discharges to less than the UV threshold, a global RESET state condition is met, as long as one regulator UV event is configured as a RESET state event (as an example, the BUCK1_UV_RST_EN bit is set to 1b) and the device goes into the RESET state. When the device goes into the RESET state, the BUCK1 regulator is enabled again (its default value). After the BUCK1 output exceeds the UV threshold, the BUCK2 regulator is enabled, followed by the BOOST converter.
    • All the BUCK1 monitoring and protection mechanisms are active, and if any critical condition is still present, the BUCK1 regulator stays disabled. If the BUCK1 regulator never recovers while in the RESET state, the RESET state time-out event puts the device in the OFF state.
  • The ENDRV/nIRQ pin is driven low.
  • The device error counter increments.

The LS MOSFET is also protected by detection circuitry for cycle-by-cycle sink-current limit. This detection circuitry protects the LS MOSFET from excessive reverse current caused by switching the PH1 or PH1A pin to PGND1 or PGND1A. If the LS sinking current exceeds the ILS_SINK_BUCK1 sink-current limit, an event is detected and the BUCK1_LS_SINK_OVC SPI status bit is set in the SAFETY_BUCK1_STAT1 register. If the event duration is longer than 20 µs (typical) the BUCK1 regulator is turned off. The inductor current continues to flow to the supply at the VIN pin through the body diode of the HS MOSFET. The BUCK1_LS_SINK_OVC_OFF_EN configuration bit setting selects the device response after the LS sink current-limit detection.

If the BUCK1_LS_SINK_OVC_OFF_EN bit is set to 1b, the following occurs:

  • The device goes into the OFF state.
  • The LS sink current limit of the BUCK1 regulator is latched in the Analog_Latch (to preserve it) while the device is in the OFF state and presented to the system MCU during the next power-up event from the OFF state.

If the BUCK1_LS_SINK_OVC_OFF_EN bit is set to 0b, the following occurs:

  • The device goes into the SAFE state with all switched-mode regulators disabled and with the resistive discharge circuit disabled.
  • The ENDRV/nIRQ pin is driven low to interrupt the system MCU.
  • The device error counter increments.

The LS sink current-limit event can also be detected when the regulator is enabled and when its output has not been discharged to less than the voltage level defined by the VBUCK1_RESTART_LEVEL voltage. Therefore, the LS sink current-limit event is masked when the BUCK1 regulator is enabled, until the BUCK1 output voltage (VBUCK1) exceeds its UV-threshold level.

GUID-71016996-6516-4E52-A850-4F9FD8D36A39-low.gif
  1. When the BUCK1 load current continues to increase to greater than the maximum specified load, an UV event can occur.
Figure 11-1 The Wide-VIN BUCK1 Short-Circuit Event