ZHCSP40B October   2021  – June 2022 LMX2571-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differences Between the LMX2571 and LMX2571-EP
      2. 7.3.2  Reference Oscillator Input
      3. 7.3.3  R-Dividers and Multiplier
      4. 7.3.4  PLL Phase Detector and Charge Pump
        1. 7.3.4.1 CPout Pin Charge Pump Current
        2. 7.3.4.2 Charge Pump Current When Using External VCO
      5. 7.3.5  PLL N-Divider and Fractional Circuitry
      6. 7.3.6  Partially Integrated Loop Filter
      7. 7.3.7  Low-Noise, Fully Integrated VCO
      8. 7.3.8  External VCO Support
      9. 7.3.9  Programmable RF Output Divider
      10. 7.3.10 Programmable RF Output Buffer
      11. 7.3.11 Integrated TX, RX Switch
      12. 7.3.12 Power Down
      13. 7.3.13 Lock Detect
      14. 7.3.14 FSK Modulation
      15. 7.3.15 FastLock
      16. 7.3.16 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Duplex Mode
      3. 7.4.3 FSK Mode
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1  R60 Register (offset = 3Ch) [reset = 4000h]
      2. 7.6.2  R58 Register (offset = 3Ah) [reset = C00h]
      3. 7.6.3  R53 Register (offset = 35h) [reset = 2802h]
      4. 7.6.4  R47 Register (offset = 2Fh) [reset = 0h]
      5. 7.6.5  R46 Register (offset = 2Eh) [reset = 1Ah]
      6. 7.6.6  R42 Register (offset = 2Ah) [reset = 210h]
      7. 7.6.7  R41 Register (offset = 29h) [reset = 810h]
      8. 7.6.8  R40 Register (offset = 28h) [reset = 101Ch]
      9. 7.6.9  R39 Register (offset = 27h) [reset = 11F0h]
      10. 7.6.10 R35 Register (offset = 23h) [reset = 647h]
      11. 7.6.11 R34 Register (offset = 22h) [reset = 1000h]
      12. 7.6.12 R33 Register (offset = 21h) [reset = 0h]
      13. 7.6.13 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]
      14. 7.6.14 R24 Register (offset = 18h) [reset = 10h]
      15. 7.6.15 R23 Register (offset = 17h) [reset = 10A4h]
      16. 7.6.16 R22 Register (offset = 16h) [reset = 8584h]
      17. 7.6.17 R21 Register (offset = 15h) [reset = 101h]
      18. 7.6.18 R20 Register (offset = 14h) [reset = 28h]
      19. 7.6.19 R19 Register (offset = 13h) [reset = 0h]
      20. 7.6.20 R18 Register (offset = 12h) [reset = 0h]
      21. 7.6.21 R17 Register (offset = 11h) [reset = 0h]
      22. 7.6.22 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]
      23. 7.6.23 R8 Register (offset = 8h) [reset = 10h]
      24. 7.6.24 R7 Register (offset = 7h) [reset = 10A4h]
      25. 7.6.25 R6 Register (offset = 6h) [reset = 8584h]
      26. 7.6.26 R5 Register (offset = 5h) [reset = 101h]
      27. 7.6.27 R4 Register (offset = 4h) [reset = 28h]
      28. 7.6.28 R3 Register (offset = 3h) [reset = 0h]
      29. 7.6.29 R2 Register (offset = 2h) [reset = 0h]
      30. 7.6.30 R1 Register (offset = 1h) [reset = 0h]
      31. 7.6.31 R0 Register (offset = 0h) [reset = 3h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Direct Digital FSK Modulation
      2. 8.1.2  Frequency and Output Port Switching
      3. 8.1.3  OSCin Configuration
      4. 8.1.4  Register R0 F1F2_INIT, F1F2_MODE Usage
      5. 8.1.5  FastLock With External VCO
      6. 8.1.6  OSCin Slew Rate
      7. 8.1.7  RF Output Buffer Power Control
      8. 8.1.8  RF Output Buffer Type
      9. 8.1.9  MULT Multiplier
      10. 8.1.10 Integrated VCO
    2. 8.2 Typical Applications
      1. 8.2.1 Synthesizer Duplex Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Synthesizer Duplex Mode Application Curves
      2. 8.2.2 PLL Duplex Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 PLL Duplex Mode Application Curves
      3. 8.2.3 Synthesizer/PLL Duplex Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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8.2.1.2 Detailed Design Procedure

First of all, calculate all the frequencies in each functional block.

GUID-52FE605A-DD08-4570-B5CC-25976EF1FC8C-low.gifFigure 8-13 F1 Frequency Plan

Assign F1 frequency to be 902 MHz. With CHDIV1 = 5 and CHDIV2 = 1, the total division is 5. As a result, the VCO frequency will be 902 × 5 = 4510 MHz, which is within the VCO tuning range.

OSCin is 26 MHz, put Pre-divider = 1 to meet the MULT input frequency range requirement.

To meet the maximum MULT output frequency requirement, possible MULT values are 3 to 5. Play around the allowable MULT values and Post-divider values to get the optimum phase noise and spurs performance. Assuming MULT = 4 and Post-divider = 1 returns the best performance, then fPD = 104 MHz.

N-divider = 21.68269231, that means Ninteger = 21 while Nfrac = 0.68269231. To use the direct digital modulation feature, put fractional denominator, DEN = 0. The actual DEN value is, in fact, equal to 224 = 16777216. So the fractional numerator, NUM, is equal to Nfrac × DEN = 11453676.

Use Equation 4 and Equation 6 to calculate the required FSK steps. For +10-kHz frequency deviation, the FSK step value is equal to [10000 × 16777216 / (104 × 106)] × (5 × 1 / 2) = 4033. For –10-kHz frequency deviation, the FSK step value is equal to 2's complement of 4033 = 61502. Similarly, the FSK step values for ±30-kHz frequency deviation are 12099 and 53436.

All the required configuration values for F2, 928 MHz can be calculated in the similar fashion and are summarized as follows:

Table 8-8 Frequency Plan Summary
CONFIGURATION PARAMETERF1 (902 MHz)F2 (928 MHz)
Pre-divider11
MULT44
Post-divider11
PDF104 MHz104 MHz
VCO4510 MHz4640 MHz
N-divider21.6826923122.30769231
Ninteger2122
DEN00
NUM114536765162220
CHDIV155
CHDIV211
FSK_DEV04033
FSK_DEV112099
FSK_DEV261502
FSK_DEV353436

Assume here that the base charge pump current = 1250 µA, CP Gain = 1x and 3rd order Delta Sigma Modulator without dithering is adopted in both frequency sets. The register settings are summarized as follows:

Table 8-9 Register Settings Summary
CONFIGURATION PARAMETERSREGISTER BITCOMMON SETTINGF1 SPECIFIC SETTINGF2 SPECIFIC SETTING
VCO calibrationFCAL_EN1 = Enabled
Lock detectSDO_LE_SEL1 = Lock detect output
LD_EN1 = Enabled
DitheringDITHERING0 = Disabled
Charge pump gainCP_GAIN1 = 1x
Base charge pump currentCP_IUP8 = 1250 µA
CP_IDN8 = 1250 µA
MULT settling timeMULT_WAIT520 = 20 µs
Output buffer typeOUTBUF_RX_TYPE1 = Push pull
OUTBUF_TX_TYPE1 = Push pull
Output buffer auto muteOUTBUF_AUTOMUTE0 = Disabled
Enable F1 F2 initializationF1F2_MODE1 = Enabled
Pre-dividerPLL_R_PRE_F11
PLL_R_PRE_F21
MULT multiplierMULT_F14
MULT_F24
Post-dividerPLL_R_F11
PLL_R_F21
ΔΣ modulator orderFRAC_ORDER_F13 = 3rd order
FRAC_ORDER_F23 = 3rd order
PFD delayPFD_DELAY_F15 = 8 clock cycles
PFD_DELAY_F25 = 8 clock cycles
CHDIV1 dividerCHDIV1_F11 = Divide by 5
CHDIV1_F21 = Divide by 5
CHDIV2 dividerCHDIV2_F10 = Divide by 1
CHDIV2_F20 = Divide by 1
Internal 3rd pole loop filterLF_R3_F14 = 800 Ω
LF_R3_F24 = 800 Ω
Internal 4th pole loop filterLF_R4_F14 = 800 Ω
LF_R4_F24 = 800 Ω
Output port selectionOUTBUF_TX_EN_F11 = TX port enabled
OUTBUF_RX_EN_F21 = RX port enabled
Output power controlOUTBUF_TX_PWR_F16
OUTBUF_RX_PWR_F26
FSK modeFSK_MODE_SEL1
FSK_MODE_SEL0		00 = FSK PIN mode
FSK levelFSK_LEVEL2 = 4FSK
Enable FSK modulationFSK_EN_F11 = Enabled
FSK deviation at 00FSK_DEV0_F14033 = +10 kHz
FSK deviation at 01FSK_DEV1_F112099 = +30 kHz
FSK deviation at 10FSK_DEV2_F161502 = -10 kHz
FSK deviation at 11FSK_DEV3_F153436 = -30 kHz
Fractional denominatorPLL_DEN_F1[23:16]0
PLL_DEN_F1[15:0]0
PLL_DEN_F2[23:16]0
PLL_DEN_F2[15:0]0
Fractional numeratorPLL_NUM_F1[23:16]174
PLL_NUM_F1[15:0]50412
PLL_NUM_F2[23:16]78
PLL_NUM_F2[15:0]50412
NintegerPLL_N_F121
PLL_N_F222
PrescalerPLL_N_PRE_F10 = Divide by 2
PLL_N_PRE_F20 = Divide by 2