ZHCSP40B October   2021  – June 2022 LMX2571-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differences Between the LMX2571 and LMX2571-EP
      2. 7.3.2  Reference Oscillator Input
      3. 7.3.3  R-Dividers and Multiplier
      4. 7.3.4  PLL Phase Detector and Charge Pump
        1. 7.3.4.1 CPout Pin Charge Pump Current
        2. 7.3.4.2 Charge Pump Current When Using External VCO
      5. 7.3.5  PLL N-Divider and Fractional Circuitry
      6. 7.3.6  Partially Integrated Loop Filter
      7. 7.3.7  Low-Noise, Fully Integrated VCO
      8. 7.3.8  External VCO Support
      9. 7.3.9  Programmable RF Output Divider
      10. 7.3.10 Programmable RF Output Buffer
      11. 7.3.11 Integrated TX, RX Switch
      12. 7.3.12 Power Down
      13. 7.3.13 Lock Detect
      14. 7.3.14 FSK Modulation
      15. 7.3.15 FastLock
      16. 7.3.16 Register Readback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
      2. 7.4.2 Duplex Mode
      3. 7.4.3 FSK Mode
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1  R60 Register (offset = 3Ch) [reset = 4000h]
      2. 7.6.2  R58 Register (offset = 3Ah) [reset = C00h]
      3. 7.6.3  R53 Register (offset = 35h) [reset = 2802h]
      4. 7.6.4  R47 Register (offset = 2Fh) [reset = 0h]
      5. 7.6.5  R46 Register (offset = 2Eh) [reset = 1Ah]
      6. 7.6.6  R42 Register (offset = 2Ah) [reset = 210h]
      7. 7.6.7  R41 Register (offset = 29h) [reset = 810h]
      8. 7.6.8  R40 Register (offset = 28h) [reset = 101Ch]
      9. 7.6.9  R39 Register (offset = 27h) [reset = 11F0h]
      10. 7.6.10 R35 Register (offset = 23h) [reset = 647h]
      11. 7.6.11 R34 Register (offset = 22h) [reset = 1000h]
      12. 7.6.12 R33 Register (offset = 21h) [reset = 0h]
      13. 7.6.13 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]
      14. 7.6.14 R24 Register (offset = 18h) [reset = 10h]
      15. 7.6.15 R23 Register (offset = 17h) [reset = 10A4h]
      16. 7.6.16 R22 Register (offset = 16h) [reset = 8584h]
      17. 7.6.17 R21 Register (offset = 15h) [reset = 101h]
      18. 7.6.18 R20 Register (offset = 14h) [reset = 28h]
      19. 7.6.19 R19 Register (offset = 13h) [reset = 0h]
      20. 7.6.20 R18 Register (offset = 12h) [reset = 0h]
      21. 7.6.21 R17 Register (offset = 11h) [reset = 0h]
      22. 7.6.22 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]
      23. 7.6.23 R8 Register (offset = 8h) [reset = 10h]
      24. 7.6.24 R7 Register (offset = 7h) [reset = 10A4h]
      25. 7.6.25 R6 Register (offset = 6h) [reset = 8584h]
      26. 7.6.26 R5 Register (offset = 5h) [reset = 101h]
      27. 7.6.27 R4 Register (offset = 4h) [reset = 28h]
      28. 7.6.28 R3 Register (offset = 3h) [reset = 0h]
      29. 7.6.29 R2 Register (offset = 2h) [reset = 0h]
      30. 7.6.30 R1 Register (offset = 1h) [reset = 0h]
      31. 7.6.31 R0 Register (offset = 0h) [reset = 3h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Direct Digital FSK Modulation
      2. 8.1.2  Frequency and Output Port Switching
      3. 8.1.3  OSCin Configuration
      4. 8.1.4  Register R0 F1F2_INIT, F1F2_MODE Usage
      5. 8.1.5  FastLock With External VCO
      6. 8.1.6  OSCin Slew Rate
      7. 8.1.7  RF Output Buffer Power Control
      8. 8.1.8  RF Output Buffer Type
      9. 8.1.9  MULT Multiplier
      10. 8.1.10 Integrated VCO
    2. 8.2 Typical Applications
      1. 8.2.1 Synthesizer Duplex Mode
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Synthesizer Duplex Mode Application Curves
      2. 8.2.2 PLL Duplex Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 PLL Duplex Mode Application Curves
      3. 8.2.3 Synthesizer/PLL Duplex Mode
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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8.1.1 Direct Digital FSK Modulation

In fractional mode, the finest delta frequency difference between two programmable output frequencies is equal to:

Equation 3. f1 – f2 = Δfmin = fPD × {[(N + 1) / DEN] – (N / DEN)} = fPD / DEN

In other words, when the fractional numerator is incremented by 1 (one step), the output frequency will change by Δfmin. A two steps increment will therefore change the frequency by 2 × Δfmin.

In FSK operation, the instantaneous carrier frequency is kept changing among some pre-defined frequencies. In general, the instantaneous carrier frequency is defined as a certain frequency deviation from the nominal carrier frequency. The frequency deviation could be positive and negative.

GUID-E288DF67-92E1-494B-ACD7-BBDD357F8058-low.gifFigure 8-1 General FSK Definition
GUID-B4FB377F-2447-4B82-B831-794C61371F66-low.gifFigure 8-2 Typical 4FSK Definition

The following equations define the number of steps required for the desired frequency deviation with respect to the nominal carrier frequency output at the RFoutTx or RFoutRx port.

Table 8-1 FSK Step Equations
POLARITYSYNTHESIZER MODEPLL MODE
POSITIVE SWING
Equation 4. GUID-1E36B18D-435B-46B0-86A9-F114BC2011F7-low.gif
Equation 5. GUID-E601105A-FA1C-4B81-99DE-03F395BA9B25-low.gif
NEGATIVE SWING
Equation 6. 2's complement of Equation 4
Equation 7. 2's complement of Equation 5

In FSK PIN mode and FSK SPI mode, register R25-32 and R9-16 are used to store the desired FSK frequency deviations in term of the number of step as defined in the above equations. The order of the registers, 0 to 7, depends on the application system. Figure 8-2 shows a typical 4FSK definition. In this case, FSK_DEV0_Fx and FSK_DEV1_Fx shall be calculated using Equation 4 or Equation 5 while FSK_DEV2_Fx and FSK_DEV3_Fx shall be calculated using Equation 6 or Equation 7.

For example, if FSK PIN mode is enabled in F1 to support 4FSK modulation, set
FSK_MODE_SEL1 = 0
FSK_MODE_SEL0 = 0
FSK_LEVEL = 2
FSK_EN_F1 = 1

Table 8-2 FSK PIN Mode Example
RAW FSK DATA STREAM INPUTEQUIVALENT SYMBOL INPUTREGISTER SELECTEDRF OUTPUT
GUID-64E8E98B-CA53-4A53-A383-4E180B14D014-low.gif10FSK_DEV2_F1GUID-414BDEC9-2BF4-439C-B5FB-C03E864EA273-low.gif
11FSK_DEV3_F1
10FSK_DEV2_F1
11FSK_DEV3_F1
01FSK_DEV1_F1
00FSK_DEV0_F1
......

FSK SPI mode assumes the user knows which symbol to send; user can directly write to register R34, FSK_DEV_SEL to select the desired frequency deviation.

For example, to enable the device to support 4FSK modulation at F1 using FSK SPI mode, set
FSK_MODE_SEL1 = 0
FSK_MODE_SEL0 = 1
FSK_LEVEL = 2
FSK_EN_F1 = 1

Table 8-3 FSK SPI Mode Example
DESIRED SYMBOLWRITE REGISTER FSK_DEV_SELREGISTER SELECTED
102FSK_DEV2_F1
113FSK_DEV3_F1
102FSK_DEV2_F1
113FSK_DEV3_F1
011FSK_DEV1_F1
000FSK_DEV0_F1
......…

Both the FSK PIN mode and FSK SPI mode support up to 8 levels of FSK. To support an arbitrary-level FSK, use FSK SPI FAST mode or FSK I2S mode. Constructing pulse-shaping FSK modulation by over-sampling the FSK modulation waveform is one of the use cases of these modes.

Analog-FM modulation can also be produced in these modes. For example, with a 1-kHz sine wave modulation signal with peak frequency deviation of ±2 kHz, the signal can be over-sampled, say 10 times. Each sample point corresponding to a scaled frequency deviation.

GUID-071115CB-3A11-4060-A738-104BBF83E696-low.gifFigure 8-3 Over-Sampling Modulation Signal

In FSK SPI FAST mode, write the desired FSK steps directly to register R33, FSK_DEV_SPI_FAST. To enable this mode, set
FSK_MODE_SEL1 = 1
FSK_MODE_SEL0 = 1
FSK_EN_F1 = 1

Table 8-4 FSK SPI FAST Mode Example
TIMEFREQUENCY DEVIATIONCORRESPONDING FSK STEPS(1)BINARY EQUIVALENTWRITE TO FSK_DEV_SPI_FAST
t0618.034 Hz5180000 0010 0000 0110518
t11618.034 Hz13570000 0101 0100 11011357
t22000 Hz16780000 0110 1000 11101678
……………
t6–1618.034 Hz641781111 1010 1011 001064178
t7–2000 Hz638571111 1001 0111 000163857
……………
(1) Synthesizer mode, fVCO = 4800 MHz, fOUT = 480 MHz, fPD = 100 MHz, Prescaler = 2, DEN = 224, Use Equation 4 and Equation 6 to calculate the step value.

In FSK I2S mode, clock in the desired binary format FSK steps in the FSK_D1 pin.

GUID-1A2E8281-8470-41CB-961A-4479743EED0C-low.gifFigure 8-4 FSK I2S Mode Example

To enable FSK I2S mode, set
FSK_MODE_SEL1 = 1
FSK_MODE_SEL0 = 0
FSK_EN_F1 =1