ZHCSNF1 February   2021 BQ25960

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charging System
      2. 9.3.2  Battery Charging Profile
      3. 9.3.3  Device Power Up
      4. 9.3.4  Device HIZ State
      5. 9.3.5  Dual Input Bi-Directional Power Path Management
        1. 9.3.5.1 ACDRV Turn-On Condition
        2. 9.3.5.2 Single Input from VAC to VBUS without ACFET-RBFET
        3. 9.3.5.3 Single Input with ACFET1
        4. 9.3.5.4 Dual Input with ACFET1-RBFET1
        5. 9.3.5.5 Dual Input with ACFET1-RBFET1 and ACFET2-RBFET2
        6. 9.3.5.6 OTG and Reverse TX Mode Operation
      6. 9.3.6  Bypass Mode Operation
      7. 9.3.7  Charging Start-Up
      8. 9.3.8  Adapter Removal
      9. 9.3.9  Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
      10. 9.3.10 Device Modes and Protection Status
        1. 9.3.10.1 Input Overvoltage, Overcurrent, Undercurrent, Reverse-Current and Short-Circuit Protection
        2. 9.3.10.2 Battery Overvoltage and Overcurrent Protection
        3. 9.3.10.3 IC Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
      11. 9.3.11 INT Pin, STAT, FLAG, and MASK Registers
      12. 9.3.12 Dual Charger Operation Using Primary and Secondary Modes
      13. 9.3.13 CDRVH and CDRVL_ADDRMS Functions
    4. 9.4 Programming
      1. 9.4.1 F/S Mode Protocol
    5. 9.5 Register Maps
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Standalone Application Information (for use with main charger)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

9.3.10.1 Input Overvoltage, Overcurrent, Undercurrent, Reverse-Current and Short-Circuit Protection

Input overvoltage protection with external single or back-to-back N-channel FET(s): The device integrates the functionality of an input overvoltage protector. With external single or back-to-back N-channel FET(s), the device blocks high input voltage exceeding VACOVP threshold (VAC1OVP or VAC2OVP). This eliminates the need for a separate OVP device to protect the overall system. The integrated VACOVP feature has a response time of tVACOVP (the actual time to turn off external FET(s) will be longer and depends upon the FET(s) gate capacitance). The VAC1OVP and VAC2OVP setting is adjustable in the VAC control register. The part allows the user to have different VAC1OVP and VAC2OVP settings. Always put the high VACOVP threshold input to VAC1.

When VAC1OVP or VAC2OVP is tripped, corresponding ACDRV is turned off and VAC1OVP_STAT or VAC2OVP_STAT and VAC1OVP_FLAG or VAC2OVP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by VAC1OVP_MASK or VAC2OVP_MASK). When VAC2OVP is triggered, the device sends multiple interrupts when the fault persists. Use VAC1 as input unless both VAC1 and VAC2 are needed.

Input overvoltage protection (BUSOVP): The BUSOVP threshold is adjustable in the BUSOVP register. When BUSOVP is tripped, switched cap or bypass mode is disabled and CHG_EN is set to ‘0’. BUSOVP_STAT and BUSOVP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSOVP_MASK). The start-up sequence must be followed to resume charging.

Input overcurrent protection (BUSOCP): Input overcurrent protection monitors the current flow into VBUS. The overcurrent protection threshold is adjustable in the BUSOCP register. When BUSOCP is tripped, Switched Cap or Bypass Mode is disabled and CHG_EN is set to ‘0’. BUSOCP_STAT and BUSOCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSOCP_MASK). The start-up sequence must be followed to resume charging.

Input undercurrent protection (BUSUCP): BUS undercurrent protection (UCP) is implemented to detect adapter unplug. Set BUSUCP =1 (REG05[6]) before enable charge. When BUSUCP is enabled (BUSUCP_DIS=0), if the current is below BUSUCP after soft start timer (programmable in SS_TIMEOUT[2:0]) expires, Switched Cap or Bypass Mode is disabled and CHG_EN is set to ‘0’. BUSUCP_STAT and BUSUCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSUCP_MASK). The start-up sequence must be followed to resume charging. The deglitch time for BUSUCP is programmable in IBUSUCP_FALL_DG_SET[1:0] register. Please note that BUSUCP deglitch time needs to be set shorter than soft start timer in order for BUSUCP to be effective.

When BUSUCP is disabled (BUSUCP_DIS=1), if the current is below BUSUCP after soft-start timer expires, CHG_EN is not set to ‘0’, BUSUCP_STAT and BUSUCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSUCP_MASK). The host can determine if charge needs to be stopped in this case.

Input reverse-current protection (BUSRCP): The device monitors the current flow from VBUS to VBAT to ensure there is no reverse current (current flow from VBAT to VBUS). In an event that a reverse current flow is detected when BUSRCP_DIS is set to ‘0’, the Switched Cap or Bypass is disabled and CHG_EN is set to ‘0’. The start-up sequence must be followed to resume charging. To disable BUSRCP, set REG05[1:0] to '00' and then set BUSRCP_DIS=1.

RCP is always active when converter is switching and BUSRCP_DIS is set to '0'. When RCP is tripped, BUSRCP_STAT and BUSRCP_FLAG is set to ‘1’, and INT is asserted low to alert the host (unless masked by BUSRCP_MASK).

Input overvoltage and overcurrent protection alarm (BUSOVP_ALM and BUSOCP_ALM): In addition to input overvoltage and overcurrent, the device also integrates alarm function BUSOVP_ALM and BUSOCP_ALM. When alarm is triggered, the corresponding STAT and FLAG bit is set to ‘1’ and INT is asserted low to alert the host (unless it is masked by the MASK bit). However, CHG_EN is not cleared and host can reduce input voltage or input current to prevent VBUS reaching VBUSOVP threshold or IBUS reaching IBUSOCP threshold.

VBUS_ERRHI: the device monitors VBUS to VOUT voltage ratio. If VBUS/VOUT is greater than VBUS_ERRHI_RISING threshold, the converter does not switch but CHG_EN is kept at '1'. The converter automatically starts switching when the VBUS/VOUT drops below VBUS_ERRHI_FALLING threshold.