ZHCSNF1 February   2021 BQ25960

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charging System
      2. 9.3.2  Battery Charging Profile
      3. 9.3.3  Device Power Up
      4. 9.3.4  Device HIZ State
      5. 9.3.5  Dual Input Bi-Directional Power Path Management
        1. 9.3.5.1 ACDRV Turn-On Condition
        2. 9.3.5.2 Single Input from VAC to VBUS without ACFET-RBFET
        3. 9.3.5.3 Single Input with ACFET1
        4. 9.3.5.4 Dual Input with ACFET1-RBFET1
        5. 9.3.5.5 Dual Input with ACFET1-RBFET1 and ACFET2-RBFET2
        6. 9.3.5.6 OTG and Reverse TX Mode Operation
      6. 9.3.6  Bypass Mode Operation
      7. 9.3.7  Charging Start-Up
      8. 9.3.8  Adapter Removal
      9. 9.3.9  Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
      10. 9.3.10 Device Modes and Protection Status
        1. 9.3.10.1 Input Overvoltage, Overcurrent, Undercurrent, Reverse-Current and Short-Circuit Protection
        2. 9.3.10.2 Battery Overvoltage and Overcurrent Protection
        3. 9.3.10.3 IC Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
      11. 9.3.11 INT Pin, STAT, FLAG, and MASK Registers
      12. 9.3.12 Dual Charger Operation Using Primary and Secondary Modes
      13. 9.3.13 CDRVH and CDRVL_ADDRMS Functions
    4. 9.4 Programming
      1. 9.4.1 F/S Mode Protocol
    5. 9.5 Register Maps
      1. 9.5.1 I2C Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Standalone Application Information (for use with main charger)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方产品免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information

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订购信息

12.1 Layout Guidelines

Layout is very important to maximize the electrical and thermal performance of the total system. General guidelines are provided, but the form factor, board stack-up, and proximity of other components also need to be considered to maximize the performance.

  1. VBUS and VOUT traces should be as short and wide as possible to accommodate for high current.
  2. Copper trace of VBUS and VOUT should run at least 150 mil (3.81 mm) straight (perpendicular to WCSP ball array) before making turns.
  3. CFLY caps should be placed as close as possible to the device and CFLY trace should be as wide as possible until close to the IC.
  4. CLFY pours should be as symmetrical between CFH pads and CFL pads as possible.
  5. Place low ESR bypass capacitors to ground for VBUS, PMID, and VOUT. The capacitor should be placed as close to the device pins as possible.
  6. The CFLY pads should be as small as possible, and the CFLY caps placed as close as possible to the device, as these are switching pins and this will help reduce EMI.
  7. Do not route so the power planes are interrupted by signal traces.

Refer to the EVM design and more information in the BQ25960EVM (BMS041) Evaluation Module User's Guide for the recommended component placement with trace and via locations.