ZHCSNF1 February 2021 BQ25960
PRODUCTION DATA
The first step is to determine the number of CFLY caps to put on each phase of the design. It is important to consider the current rating of the caps, their ESR, and the capacitance rating. Be sure to consider the bias voltage derating for the caps, as the CFLY caps are biased to half of the input voltage, and this will affect their effective capacitance. An optimal system will have 3 22-µF caps per phase, for a total of 6 caps per device. It is possible to use fewer caps if the board space is limited. Using fewer caps will result in higher voltage and current ripple on the output, as well as lower efficiency.
The default switching frequency, fSW, for the power stage is 500 kHz. The switching frequency can be adjusted in register 0x10h using the FSW_SET bits. It is recommended to select 500 kHz if IBATADC is not used and 375 kHz if IBATADC is used.
It is recommended to use 1-µF cap on VBUS, 10-µF cap on PMID and 22-µF cap on VOUT.