ZHCSNF1 February 2021 BQ25960
PRODUCTION DATA
Table 9-7 lists the I2C registers. All register offset addresses not listed in Table 9-7 should be considered as reserved locations and the register contents should not be modified. All register bits marked 'RESERVED' in Field column should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0h | REG00_BATOVP | BATOVP | Go |
| 1h | REG01_BATOVP_ALM | BATOVP_ALM | Go |
| 2h | REG02_BATOCP | BATOCP | Go |
| 3h | REG03_BATOCP_ALM | BATOCP_ALM | Go |
| 4h | REG04_BATUCP_ALM | BATUCP_ALM | Go |
| 5h | REG05_CHARGER_CONTROL 1 | CHARGER_CONTROL 1 | Go |
| 6h | REG06_BUSOVP | BUSOVP | Go |
| 7h | REG07_BUSOVP_ALM | BUSOVP_ALM | Go |
| 8h | REG08_BUSOCP | BUSOCP | Go |
| 9h | REG09_BUSOCP_ALM | BUSOCP_ALM | Go |
| Ah | REG0A_TEMP_CONTROL | TEMP CONTROL | Go |
| Bh | REG0B_TDIE_ALM | TDIE_ALM | Go |
| Ch | REG0C_TSBUS_FLT | TSBUS_FLT | Go |
| Dh | REG0D_TSBAT_FLT | TSBAT_FLT | Go |
| Eh | REG0E_VAC_CONTROL | VAC CONTROL | Go |
| Fh | REG0F_CHARGER_CONTROL 2 | CHARGER CONTROL 2 | Go |
| 10h | REG10_CHARGER_CONTROL 3 | CHARGER CONTROL 3 | Go |
| 11h | REG11_CHARGER_CONTROL 4 | CHARGER CONTROL 4 | Go |
| 12h | REG12_CHARGER_CONTROL 5 | CHARGER CONTROL 5 | Go |
| 13h | REG13_STAT 1 | STAT 1 | Go |
| 14h | REG14_STAT 2 | STAT 2 | Go |
| 15h | REG15_STAT 3 | STAT 3 | Go |
| 16h | REG16_STAT 4 | STAT 4 | Go |
| 17h | REG17_STAT 5 | STAT 5 | Go |
| 18h | REG18_FLAG 1 | FLAG 1 | Go |
| 19h | REG19_FLAG 2 | FLAG 2 | Go |
| 1Ah | REG1A_FLAG 3 | FLAG 3 | Go |
| 1Bh | REG1B_FLAG 4 | FLAG 4 | Go |
| 1Ch | REG1C_FLAG 5 | FLAG 5 | Go |
| 1Dh | REG1D_MASK 1 | MASK 1 | Go |
| 1Eh | REG1E_MASK 2 | MASK 2 | Go |
| 1Fh | REG1F_MASK 3 | MASK 3 | Go |
| 20h | REG20_MASK 4 | MASK 4 | Go |
| 21h | REG21_MASK 5 | MASK 5 | Go |
| 22h | REG22_DEVICE_INFO | DEVICE INFO | Go |
| 23h | REG23_ADC_CONTROL 1 | ADC_CONTROL 1 | Go |
| 24h | REG24_ADC_CONTROL 2 | ADC_CONTROL 2 | Go |
| 25h | REG25_IBUS_ADC | IBUS_ADC | Go |
| 27h | REG27_VBUS_ADC | VBUS_ADC | Go |
| 29h | REG29_VAC1_ADC | VAC1_ADC | Go |
| 2Bh | REG2B_VAC2_ADC | VAC2_ADC | Go |
| 2Dh | REG2D_VOUT_ADC | VOUT_ADC | Go |
| 2Fh | REG2F_VBAT_ADC | VBAT_ADC | Go |
| 31h | REG31_IBAT_ADC | IBAT_ADC | Go |
| 33h | REG33_TSBUS_ADC | TSBUS_ADC | Go |
| 35h | REG35_TSBAT_ADC | TSBAT_ADC | Go |
| 37h | REG37_TDIE_ADC | TDIE_ADC | Go |
Complex bit access types are encoded to fit into small table cells. Table 9-8 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
REG00_BATOVP is shown in Table 9-9
Return to the Summary Table.
BATOVP
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BATOVP_DIS | R/W | 0h | Reset by: REG_RST | Disable BATOVP Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6-0 | BATOVP_6:0 | R/W | 5Ah | Reset by: REG_RST | Battery Overvoltage Setting. When the battery voltage reaches the
programmed threshold, QB and switching FETs are turned off and CHG_EN is
set to '0'. The host controller should monitor the bus voltage to ensure that the
adapter keeps the voltage under the BATOVP threshold for proper operation. Type : R/W POR: 4390 mV (5Ah) Range : 3491 mV - 4759 mV Fixed Offset : 3491 mV Bit Step Size : 9.985 mV |
REG01_BATOVP_ALM is shown in Table 9-10.
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BATOVP_ALM
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BATOVP_ALM_DIS | R/W | 0h | Reset by: REG_RST | Disable BATOVP_ALM Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6-0 | BATOVP_ALM_6:0 | R/W | 46h | Reset by: REG_RST | When battery voltage goes above the programmed threshold, an
INT is sent. The BATOVP_ALM should be set lower than BATOVP and the host controller should monitor the battery voltage to ensure that the adapter keeps the voltage under BATOVP threshold for proper operation. Type : R/W POR: 4200 mV (46h) Range : 3500 mV - 4770 mV Fixed Offset : 3500 mV Bit Step Size : 10 mV |
REG02_BATOCP is shown in Table 9-11.
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BATOCP
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BATOCP_DIS | R/W | 0h | Reset by: REG_RST | Disable BATOCP Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6-0 | BATOCP_6:0 | R/W | 47h | Reset by: REG_RST | Battery Overcurrent Protection Setting. When battery current reaches
the programmed threshold, the QB and switching FETs are disabled and
CHG_EN is set to '0'. The host controller should monitor the battery current to
ensure that the adapter keeps the current under the threshold for proper
operation. Type : R/W POR: 7277.5 mA (47h) Range : 2050 mA - 8712.5 mA Fixed Offset : 0 mA Bit Step Size : 102.5 mA |
REG03_BATOCP_ALM is shown in Table 9-12.
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BATOCP_ALM
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BATOCP_ALM_DIS | R/W | 0h | Reset by: REG_RST | Disable BATOCP_ALM Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6-0 | BATOCP_ALM_6:0 | R/W | 46h | Reset by: REG_RST | Battery Overcurrent Alarm Setting. When battery current reaches the
programmed threshold, an INT is sent. The BATOCP_ALM should be set lower than BATOCP and the host controller should monitor the battery current to ensure that the adapter keeps the current under BATOCP threshold for proper operation. Type : R/W POR: 7000 mA (46h) Range : 0 mA - 12700 mA Fixed Offset : 0 mA Bit Step Size : 100 mA |
REG04_BATUCP_ALM is shown in Table 9-13.
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BATUCP_ALM
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BATUCP_ALM_DIS | R/W | 0h | Reset by: REG_RST | Disable BATUCP_ALM Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6-0 | BATUCP_ALM_6:0 | R/W | 28h | Reset by: REG_RST | Battery Undercurrent Alarm setting. When battery current falls below
the programmed threshold, an INT is sent. The host controller
should monitor the battery current to determine when to disable the device and hand
over charging to the main charger. Type : R/W POR: 2000 mA (28h) Range : 0 mA - 4500 mA Fixed Offset : 0 mA Bit Step Size : 50 mA |
REG05_CHARGER_CONTRL 1 is shown in Table 9-14.
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CHARGER_CONTROL 1
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BUSUCP_DIS | R/W | 0h | Reset by: REG_RST | Disable BUSUCP Type : R/W POR: 0b 0h = Enable, BUSUCP turns off QB and switching FETs, BUSUCP_STAT and FLAG is set to '1', and INT is sent to host. 1h = Disable, BUSUCP does not turn off QB or switching FETs, but BUSUCP_STAT and FLAG is set to '1', and INT is sent to host. |
| 6 | BUSUCP | R/W | 0h | Reset by: REG_RST | BUSUCP Setting. If input current is below BUSUCP threshold after soft
start timer expires, the QB and switching FETs are turned off and CHG_EN
is set to '0' and INT is sent if BUSUCP_DIS=0. If BUSUCP_DIS=1,
INT is sent to host but converter keeps running. Change this
bit to '1' before CHG_EN is set to '1' in order for BUSUCP to be effective. Type : R/W POR: 0b 0h = RESERVED 1h = 250 mA |
| 5 | BUSRCP_DIS | R/W | 0h | Reset by: REG_RST | Disable BUSRCP Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 4 | BUSRCP | R/W | 0h | Reset by: REG_RST | BUSRCP Setting, if IBUS is below BUSRCP threshold, the QB
and switching FETs are turned off and CHG_EN is set to '0' and
INT is sent. Keep this bit set to '0' in order for BUSRCP to
be effective. Type : R/W POR: 0b 0h = 300 mA 1h = RESERVED |
| 3 | CHG_CONFIG_1 | R/W | 0h | Reset by: REG_RST | Charger Configuration 1. Set this bit to '1' before CHG_EN is set to
'1'. Type : R/W POR: 0h |
| 2 | VBUS_ERRHI_DIS | R/W | 0h | Reset by: REG_RST | Disable VBUS_ERRHI Type : R/W POR: 0b 0h = Enable, converter does not switching, but QB is turned on when device is in VBUS_ERRHI 1h = Disable, both converter and QB is turned on when device is in VBUS_ERRHI |
| 1-0 | RESERVED | R/W | 2h | Reset by: REG_RST | RESERVED Type : R/W POR: 10b |
REG06_BUSOVP is shown in Table 9-15.
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BUSOVP
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BUS_PD_EN | R/W | 0h | Reset by: REG_RST | VBUS Pulldown Resistor Control Type : R/W POR: 0b 0h = Disable 1h = Enable |
| 6-0 | BUSOVP_6:0 | R/W | 26h | Reset by: REG_RST | Bus Overvoltage Setting. When the bus voltage reaches the programmed
threshold, QB and switching FETs are turned off and CHG_EN is set to '0'.
The host controller should monitor the bus voltage to ensure that the adapter keeps
the voltage under the BUSOVP threshold for proper operation. Switched cap mode: Type : R/W POR: 8900 mV (26h) Range : 7000 mV - 12750 mV Fixed Offset : 7000 mV Bit Step Size : 50 mV Bypass Mode: Type : R/W POR: 4450 mV (26h) Range : 3500 mV - 6500 mV Fixed Offset : 3500 mV Bit Step Size : 25 mV |
REG07_BUSOVP_ALM is shown in Table 9-16.
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BUSOVP_ALM
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BUSOVP_ALM_DIS | R/W | 0h | Reset by: REG_RST | Disable BUSOVP_ALM Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6-0 | BUSOVP_ALM_6:0 | R/W | 22h | Reset by: REG_RST | Bus Overvoltage Alarm Setting. When the bus voltage reaches the
programmed threshold, an INT is sent. The host controller
should monitor the bus voltage to ensure that the adapter keeps the voltage under
the BUSOVP threshold for proper operation. Switched Cap Mode: Type : R/W POR: 8700 mV (22h) Range : 7000 mV - 13350 mV Fixed Offset : 7000 mV Bit Step Size : 50 mV Bypass Mode: Type : R/W POR: 4350 mV (22h) Range : 3500 mV - 6675 mV Fixed Offset : 3500 mV Bit Step Size : 25 mV |
REG08_BUSOCP is shown in Table 9-17.
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BUSOCP
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7-5 | RESERVED | R | 0h | RESERVED | |
| 4-0 | BUSOCP_4:0 | R/W | Bh | Reset by: REG_RST | BUS Overcurrent Protection Setting. When the bus current reaches the
programmed threshold, the output is disabled. The host controller should monitor the
bus current to ensure that the adapter keeps the current under this threshold for
proper operation. Type : R/W Switched Cap Mode: POR: 3816 mA (Bh) Range: 1017.5 mA - 4579 mA Fixed Offset : 1017.5 mA Bit Step Size : 254 mA Bypass Mode: POR: 3928 mA (Bh) Range: 1047.5 mA - 6809 mA |
REG09_BUSOCP_ALM is shown in Table 9-18.
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BUSOCP_ALM
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BUSOCP_ALM_DIS | R/W | 0h | Reset by: REG_RST | Disable BUSOCP_ALM Type : R/W POR: 0b 0h = Enable 1h = Disable |
6-5 | RESERVED | R | 0h | RESERVED | |
| 4-0 | BUSOCP_ALM_4:0 | R/W | Ah | Reset by: REG_RST | Bus Overvoltage Alarm Setting. When the
bus current reaches the programmed threshold, an INT is sent.
The host controller should monitor the bus current to ensure that the adapter keeps
the current under the BUSOCP threshold for proper operation. Type : R/W POR: 3500 mA (Ah) Range : 1000 mA - 8750 mA Fixed Offset : 1000 mA Bit Step Size : 250 mA |
REG0A_TEMP_CONTROL is shown in Table 9-19.
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TEMP_CONTROL
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | TDIE_FLT_DIS | R/W | 0h | Reset by: REG_RST | Disable TDIE Overtemperature Protection Type : R/W POR: 0b 0h = TDIE_FLT enable 1h = TDIE_FLT disable |
| 6-5 | TDIE_FLT_1:0 | R/W | 3h | Reset by: REG_RST | TDIE Overtemperature Setting. When the junction temperature reaches
the programmed threshold, the QB and switching FETs are turned off and
CHG_EN is set to '0'. Type : R/W POR: 11b 0h = 80C 1h = 100C 2h = 120C 3h = 140C |
| 4 | TDIE_ALM_DIS | R/W | 0h | Reset by: REG_RST | Disable TDIE Overtemperature Alarm Type : R/W POR: 0b 0h = TDIE_ALM enable 1h = TDIE_ALM disable |
| 3 | TSBUS_FLT_DIS | R/W | 0h | Reset by: REG_RST | Disable TSBUS_FLT Type : R/W POR: 0b 0h = TSBUS_FLT enable 1h = TSBUS_FLT disable |
| 2 | TSBAT_FLT_DIS | R/W | 0h | Reset by: REG_RST | Disable TSBAT_FLT Type : R/W POR: 0b 0h = TSBAT_FLT enable 1h = TSBAT_FLT disable |
| 1-0 | RESERVED | R | 0h | RESERVED Type : R POR: 00b |
REG0B_TDIE_ALM is shown in Table 9-20.
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TDIE_ALM
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7-0 | TDIE_ALM_7:0 | R/W | C8h | Reset by: REG_RST | Die Overtemperature Alarm Setting. When the junction temperature
reaches the programmed threshold, an INT is sent. Type : R/W POR: 125°C (C8h) Range : 25°C - 150°C Fixed Offset : 25°C Bit Step Size : 0.5°C |
REG0C_TSBUS_FLT is shown in Table 9-21.
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TSBUS_FLT
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7-0 | TSBUS_FLT_7:0 | R/W | 15h | Reset by: REG_RST | TSBUS Percentage Fault Threshold. When the TSBUS/REGN ratio drops
below the programmed threshold, the QB and switching FETs are turned off
and CHG_EN is set to '0'. Type : R/W POR: 4.10151% (15h) Range : 0% - 49.8041% Fixed Offset : 0% Bit Step Size : 0.19531% |
REG0D_TSBAT_FLG is shown in Table 9-22.
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TSBAT_FLG
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7-0 | TSBAT_FLT_7:0 | R/W | 15h | Reset by: REG_RST | TSBAT Percentage Fault Threshold. When the TSBAT/REGN ratio drops
below the programmed threshold, the QB and switching FETs are turned off
and CHG_EN is set to '0'. Type : R/W POR: 4.10151% (15h) Range : 0% - 49.8041% Fixed Offset : 0% Bit Step Size : 0.19531% |
REG0E_VAC_CONTROL is shown in Table 9-23.
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VAC_CONTROL
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7-5 | VAC1OVP_2:0 | R/W | 0h | Reset by: REG_RST | VAC1OVP Setting. When VAC1 voltage reaches the programmed threshold,
ACDRV1 is turned off. Type : R/W POR: 000b 0h = 6.5 V 1h = 10.5 V 2h = 12 V 3h = 14 V 4h = 16 V 5h = 18 V |
| 4-2 | VAC2OVP_2:0 | R/W | 0h | Reset by: REG_RST | VAC2OVP Setting. When VAC2 voltage reaches the programmed threshold,
ACDRV2 is turned off. Type : R/W POR: 000b 0h = 6.5 V 1h = 10.5 V 2h = 12 V 3h = 14 V 4h = 16 V 5h = 18 V |
| 1 | VAC1_PD_EN | R/W | 0h | Reset by: REG_RST | Enable VAC1 Pulldown Resistor Type : R/W POR: 0b 0h = Disable 1h = Enable |
| 0 | VAC2_PD_EN | R/W | 0h | Reset by: REG_RST | Enable VAC2 Pulldown Resistor Type : R/W POR: 0b 0h = Disable 1h = Enable |
REG0F_CHARGER_CONTROL 2 is shown in Table 9-24.
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CHARGER CONTROL 2
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | REG_RST | R/W | 0h | Reset by: REG_RST | Register Reset. Reset registers to default values and reset timer.
This bit automatically goes back to '0' after reset. Type : R/W POR: 0b 0h = Not reset register 1h = Reset register |
| 6 | EN_HIZ | R/W | 0h | Reset by: REG_RST | Enable HIZ Mode. When device is in HIZ mode, converter stops
switching, ADC stops converting, ACDRV is turned off and the REGN LDO is forced off.
Type : R/W POR: 0b 0h = Disable HIZ mode 1h = Enable HIZ mode |
| 5 | EN_OTG | R/W | 0h | Reset by: WATCHDOG REG_RST | Power Path Control During the OTG and Reverse TX Mode Type : R/W POR: 0b 0h = Don't allow host to control ACDRV(s) 1h = Allow host to control ACDRV(s) |
| 4 | CHG_EN | R/W | 0h | Reset by: WATCHDOG REG_RST | Charge Enable Type : R/W POR: 0b 0h = Disable charge 1h = Enable charge |
| 3 | EN_BYPASS | R/W | 0h | Reset by: WATCHDOG REG_RST | Enable Bypass Mode Type : R/W POR: 0b 0h = Disable Bypass Mode 1h = Enable Bypass Mode |
| 2 | DIS_ACDRV_BOTH | R/W | 0h | Disable Both ACDRV. When this bit is set, the device forces both
ACDRV off. It is not reset by the REG_RST or the WATCHDOG. Type : R/W POR: 0b 0h = ACDRV1 and ACDRV2 can be turned on 1h = ACDRV1 and ACDRV2 are forced off | |
| 1 | ACDRV1_STAT | R/W | 0h | External ACFET1-RBFET1 Gate Driver Status. For dual input with two
sets ACFET-RBFET, this bit can be used to swap input. It is not reset by the REG_RST
or the WATCHDOG. Type : R/W POR: 0b 0h = ACDRV1 is OFF 1h = ACDRV1 is ON | |
| 0 | ACDRV2_STAT | R/W | 0h | External ACFET2-RBFET2 Gate Driver Status. For dual input with two
sets ACFET-RBFET, this bit can be used to swap input. It is not reset by the REG_RST
or the WATCHDOG. Type : R/W POR: 0b 0h = ACDRV2 is OFF 1h = ACDRV2 is ON |
REG10_CHARGER_CONTROL 3 is shown in Table 9-25.
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CHARGER CONTROL 3
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7-5 | FSW_SET_2:0 | R/W | 4h | Set Switching Frequency in Switched Cap Mode. It is not reset by the
REG_RST or the WATCHDOG. Type : R/W POR: 100b 0h = 187.5 kHz 1h = 250 kHz 2h = 300 kHz 3h = 375 kHz 4h = 500 kHz 5h = 750 kHz The maximum switching frequency is 500 kHz in dual charger configuration. | |
| 4-3 | WATCHDOG_1:0 | R/W | 0h | Reset by: REG_RST | Watchdog Timer Type : R/W POR: 00b 0h = 0.5 s 1h = 1 s 2h = 5 s 3h = 30 s |
| 2 | WATCHDOG_DIS | R/W | 0h | Reset by: REG_RST | Watchdog Timer Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 1-0 | RESERVED | R | 3h | RESERVED |
REG11_CHARGER_CONTROL 4 is shown in Table 9-26.
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CHARGER CONTROL 4
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | RSNS | R/W | 0h | Reset by: REG_RST | Battery Current Sense Resistor Value Type : R/W POR: 0b 0h = 2 mΩ 1h = 5 mΩ |
| 6-4 | SS_TIMEOUT_2:0 | R/W | 7h | Soft Start Timeout to Check if Input Current is Above BUSUCP
Threshold. It is not reset by the REG_RST or the WATCHDOG. Type : R/W POR: 111b 0h = 6.25 ms 1h = 12.5 ms 2h = 25 ms 3h = 50 ms 4h = 100 ms 5h = 400 ms 6h = 1.5 s 7h = 10 s | |
| 3-2 | IBUSUCP_FALL_DG_SEL_1:0 | R/W | 0h | Reset by: REG_RST | BUSUCP Deglitch Timer Type : R/W POR: 00b 0h = 0.01 ms 1h = 5 ms 2h = 50 ms 3h = 150 ms |
| 1-0 | RESERVED | R/W | 1h | Reset by: REG_RST | RESERVED Type : R/W POR: 1b |
REG12_CHARGER_CONTROL 5 is shown in Table 9-27.
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CHARGER CONTROL 5
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | VOUTOVP_DIS | R/W | 0h | Reset by: REG_RST | Disable VOUTOVP Type : R/W POR: 0b 0h = Enable 1h = Disable |
6-5 | VOUTOVP_1:0 | R/W | 3h | Reset by: REG_RST | VOUTOVP Protection. When output voltage
is above the programmed threshold, QB and switching FETs are
turned off and CHG_EN is set to '0'. Type : R/W POR: 11b 0h = 4.7 V 1h = 4.8 V 2h = 4.9 V 3h = 5.0 V |
| 4-3 | FREQ_SHIFT_1:0 | R/W | 0h | Reset by: REG_RST | Adjust Switching Frequency Type : R/W POR: 00b 0h = Nominal switching frequency set in REG10[7:5] 1h = Set switching frequency 10% higher than normal 2h = Set switching frequency 10% lower than normal |
| 2 | RESERVED | R/W | 0h | Reset by: REG_RST | RESERVED Type : R/W POR: 0b |
| 1-0 | MS_1:0 | R | 0h | Primary, Secondary, Standalone Operation Type : R POR: 00b 0h = Standalone 1h = Secondary 2h = Primary |
REG13_STAT 1 is shown in Table 9-28.
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STAT 1
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BATOVP_STAT | R | 0h | BATOVP Status Type : R POR: 0b 0h = Not in BATOVP 1h = In BATOVP |
| 6 | BATOVP_ALM_STAT | R | 0h | BATOVP_ALM Status Type : R POR: 0b 0h = Not in BATOVP_ALM 1h = In BATOVP_ALM |
| 5 | VOUTOVP_STAT | R | 0h | VOUTOVP Status Type : R POR: 0b 0h = Not in VOUTOVP 1h = in VOUTOVP |
| 4 | BATOCP_STAT | R | 0h | BATOCP Status Type : R POR: 0b 0h = Not in BATOCP 1h = In BATOCP |
| 3 | BATOCP_ALM_STAT | R | 0h | BATOCP_ALM Status Type : R POR: 0b 0h = Not in BATOCP_ALM 1h = In BATOCP_ALM |
| 2 | BATUCP_ALM_STAT | R | 0h | BATUCP_ALM Status Type : R POR: 0b 0h = Not in BATUCP_ALM 1h = In BATUCP_ALM |
| 1 | BUSOVP_STAT | R | 0h | VBUSOVP Status Type : R POR: 0b 0h = Not in VBUS OVP 1h = In VBUS OVP |
| 0 | BUSOVP_ALM_STAT | R | 0h | BUSOVP_ALM Status Type : R POR: 0b 0h = Not in BUSOVP_ALM 1h = In BUSOVP_ALM |
REG14_STAT 2 is shown in Table 9-29.
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STAT 2
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUSOCP_STAT | R | 0h | BUSOCP Status Type : R POR: 0b 0h = Not in BUSOCP 1h = In BUSOCP |
| 6 | BUSOCP_ALM_STAT | R | 0h | BUSOCP_ALM Status Type : R POR: 0b 0h = Not in BUSOCP_ALM 1h = In BUSOCP_ALM |
| 5 | BUSUCP_STAT | R | 0h | BUSUCP Status Type : R POR: 0b 0h = Not in BUSUCP 1h = In BUSUCP |
| 4 | BUSRCP_STAT | R | 0h | BUSRCP Status Type : R POR: 0b 0h = Not in BUSRCP 1h = In BUSRCP |
| 3 | RESERVED | R | 0h | RESERVED |
| 2 | CFLY_SHORT_STAT | R | 0h | CFLY Short Detection Status Type : R POR: 0b 0h = CFLY not shorted 1h = CFLY shorted |
| 1-0 | RESERVED | R | 0h | RESERVED |
REG15_STAT 3 is shown in Table 9-30.
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STAT 3
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | VAC1OVP_STAT | R | 0h | VAC1 OVP Status Type : R POR: 0b 0h = Not in VAC1 OVP 1h = In VAC1 OVP |
| 6 | VAC2OVP_STAT | R | 0h | VAC2 OVP Status Type : R POR: 0b 0h = Not in VAC2 OVP 1h = In VAC2 OVP |
| 5 | VOUTPRESENT_STAT | R | 0h | VOUT Present Status Type : R POR: 0b 0h = VOUT not present 1h = VOUT present |
| 4 | VAC1PRESENT_STAT | R | 0h | VAC1 Present Status Type : R POR: 0b 0h = VAC1 not present 1h = VAC1 present |
| 3 | VAC2PRESENT_STAT | R | 0h | VAC2 Present Status Type : R POR: 0b 0h = VAC2 not present 1h = VAC2 present |
| 2 | VBUSPRESENT_STAT | R | 0h | VBUS Present Status Type : R POR: 0b 0h = VBUS not present 1h = VBUS present |
| 1 | ACRB1_CONFIG_STAT | R | 0h | ACFET1-RBFET1 Status Type : R POR: 0b 0h = ACFET1-RBFET1 is not placed 1h = ACFET1-RBFET1 is placed |
| 0 | ACRB2_CONFIG_STAT | R | 0h | ACFET2-RBFET2 Status Type : R POR: 0b 0h = ACFET2-RBFET2 is not placed 1h = ACFET2-RBFET2 is placed |
REG16_STAT 4 is shown in Table 9-31.
Return to the Summary Table.
STAT 4
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ADC_DONE_STAT | R | 0h | ADC Conversion Status (in One-Shot Mode only) Note: Always reads 0 in continuous mode Type : R POR: 0b 0h = Conversion not complete 1h = Conversion complete |
| 6 | SS_TIMEOUT_STAT | R | 0h | Soft-Start Timeout Status Type : R POR: 0b 0h = Device not in soft timeout 1h = Device in soft timeout |
| 5 | TSBUS_TSBAT_ALM_STAT | R | 0h | TSBUS and TSBAT ALM Status Type : R POR: 0b 0h = TSBUS or TSBAT threshold is NOT within 5% of the TSBUS_FLT or TSBAT_FLT set threshold 1h = TSBUS or TSBAT threshold is within 5% of the TSBUS_FLT or TSBAT_FLT set threshold |
| 4 | TSBUS_FLT_STAT | R | 0h | TSBUS_FLT Status Type : R POR: 0b 0h = Not in TSBUS_FLT 1h = In TSBUS_FLT |
| 3 | TSBAT_FLT_STAT | R | 0h | TSBAT_FLT Status Type : R POR: 0b 0h = Not in TSBAT_FLT 1h = In TSBAT_FLT |
| 2 | TDIE_FLT_STAT | R | 0h | TDIE Fault Status Type : R POR: 0b 0h = Not in TDIE fault 1h = In TDIE fault |
| 1 | TDIE_ALM_STAT | R | 0h | TDIE_ALM Status Type : R POR: 0b 0h = Not in TDIE_ALM 1h = In TDIE_ALM |
| 0 | WD_STAT | R | 0h | I2C Watch Dog Status Type : R POR: 0b 0h = Normal 1h = WD timer expired |
REG17_STAT 5 is shown in Table 9-32.
Return to the Summary Table.
STAT 5
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | REGN_GOOD_STAT | R | 0h | REGN_GOOD Status Type : R POR: 0b 0h = REGN not good 1h = REGN good |
| 6 | CONV_ACTIVE_STAT | R | 0h | Converter Active Status Type : R POR: 0b 0h = Converter not running 1h = Converter running |
| 5 | RESERVED | R | 0h | RESERVED |
| 4 | VBUS_ERRHI_STAT | R | 0h | VBUS_ERRHI Status Type : R POR: 0b 0h = Not in VBUS_ERRHI status 1h = In VBUS_ERRHI status |
| 3-0 | RESERVED | R | 0h | RESERVED |
REG18_FLAG 1 is shown in Table 9-33.
Return to the Summary Table.
FLAG 1
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BATOVP_FLAG | R | 0h | BATOVP Flag Type : R POR: 0b 0h = Normal 1h = BATOVP status changed |
| 6 | BATOVP_ALM_FLAG | R | 0h | BATOVP_ALM Flag Type : R POR: 0b 0h = Normal 1h = BATOVP_ALM status changed |
| 5 | VOUTOVP_FLAG | R | 0h | VOUTOVP Flag Type : R POR: 0b 0h = Normal 1h = VOUTOVP status changed |
| 4 | BATOCP_FLAG | R | 0h | BATOCP Flag Type : R POR: 0b 0h = Normal 1h = BATOCP status changed |
| 3 | BATOCP_ALM_FLAG | R | 0h | BATOCP_ALM Flag Type : R POR: 0b 0h = Normal 1h = BATOCP_ALM status changed |
| 2 | BATUCP_ALM_FLAG | R | 0h | BATUCP_ALM Flag Type : R POR: 0b 0h = Normal 1h = BATUCP_ALM status changed |
| 1 | BUSOVP_FLAG | R | 0h | BUSOVP Flag Type : R POR: 0b 0h = Normal 1h = BUSOVP status changed |
| 0 | BUSOVP_ALM_FLAG | R | 0h | BUSOVP_ALM Flag Type : R POR: 0b 0h = Normal 1h = BUSOVP_ALM status changed |
REG19_FLAG 2 is shown in Table 9-34.
Return to the Summary Table.
FLAG 2
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | BUSOCP_FLAG | R | 0h | BUSOCP Flag Type : R POR: 0b 0h = Normal 1h = BUSOCP status changed |
| 6 | BUSOCP_ALM_FLAG | R | 0h | BUSOCP_ALM Flag Type : R POR: 0b 0h = Normal 1h = BUSOCP_ALM status changed |
| 5 | BUSUCP_FLAG | R | 0h | BUSUCP Flag Type : R POR: 0b 0h = Normal 1h = BUSUCP status changed |
| 4 | BUSRCP_FLAG | R | 0h | BUSRCP Flag Type : R POR: 0b 0h = Normal 1h = BUSRCP status changed |
| 3 | RESERVED | R | 0h | RESERVED |
| 2 | CFLY_SHORT_FLAG | R | 0h | CFLY Short Flag Type : R POR: 0b 0h = Normal 1h = CFLY_SHORT status changed |
| 1-0 | RESERVED | R | 0h | RESERVED |
REG1A_FLAG 3 is shown in Table 9-35.
Return to the Summary Table.
FLAG 3
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | VAC1OVP_FLAG | R | 0h | VAC1OVP Flag Type : R POR: 0b 0h = Normal 1h = VAC1 OVP status changed |
| 6 | VAC2OVP_FLAG | R | 0h | VAC2OVP Flag Type : R POR: 0b 0h = Normal 1h = VAC2 OVP status changed |
| 5 | VOUTPRESENT_FLAG | R | 0h |
VOUT Present Flag 0h = Normal 1h = VOUT present status changed |
| 4 | VAC1PRESENT_FLAG | R | 0h | VAC1 Present Flag Type : R POR: 0b 0h = Normal 1h = VAC1 present status changed |
| 3 | VAC2PRESENT_FLAG | R | 0h | VAC2 Present Flag Type : R POR: 0b 0h = Normal 1h = VAC2 present status changed |
| 2 | VBUSPRESENT_FLAG | R | 0h | VBUS Present Flag Type : R POR: 0b 0h = Normal 1h = VBUS present status changed |
| 1 | ACRB1_CONFIG_FLAG | R | 0h | ACFET1-RBFET1_CONFIG Flag Type : R POR: 0b 0h = Normal 1h = ACFET1-RBFET1_CONFIG status changed |
| 0 | ACRB2_CONFIG_FLAG | R | 0h | ACFET2-RBFET2_CONFIG Flag Type : R POR: 0b 0h = Normal 1h = ACFET2-RBFET2_CONFIG status changed |
REG1B_FLAG 4 is shown in Table 9-36.
Return to the Summary Table.
FLAG 4
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | ADC_DONE_FLAG | R | 0h | ADC Conversion Flag (in One-Shot Mode only) Type : R POR: 0b 0h = Normal 1h = ADC conversion done status changed |
| 6 | SS_TIMEOUT_FLAG | R | 0h | Soft-Start Timeout Flag Type : R POR: 0b 0h = Normal 1h = Soft start timeout status changed |
| 5 | TSBUS_TSBAT_ALM_FLAG | R | 0h | TSBUS_TSBAT_ALM Flag Type : R POR: 0b 0h = Normal 1h = Converter active status changed |
| 4 | TSBUS_FLT_FLAG | R | 0h | TSBUS_FLT Flag Type : R POR: 0b 0h = Normal 1h = TSBUS_FLT status changed |
| 3 | TSBAT_FLT_FLAG | R | 0h | TSBAT_FLT Flag Type : R POR: 0b 0h = Normal 1h = TSBAT_FLT status changed |
| 2 | TDIE_FLT_FLAG | R | 0h | TDIE_FLT Flag Type : R POR: 0b 0h = Normal 1h = TDIE_FLT status changed |
| 1 | TDIE_ALM_FLAG | R | 0h | TDIE_ALM Flag Type : R POR: 0b 0h = Normal 1h = TDIE_ALM status changed |
| 0 | WD_FLAG | R | 0h | I2C Watch Dog Timer Flag Type : R POR: 0b 0h = Normal 1h = WD timer status changed |
REG1C_FLAG 5 is shown in Table 9-37.
Return to the Summary Table.
FLAG 5
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | REGN_GOOD_FLAG | R | 0h | REGN_GOOD Flag Type : R POR: 0b 0h = Normal 1h = REGN_GOOD status changed |
| 6 | CONV_ACTIVE_FLAG | R | 0h | Converter Active Flag Type : R POR: 0b 0h = Normal 1h = Converter active status changed |
| 5 | RESERVED | R | 0h | RESERVED |
| 4 | VBUS_ERRHI_FLAG | R | 0h | VBUS_ERRHI Flag Type : R POR: 0b 0h = Normal 1h = VBUS_ERRHI status changed |
| 3-0 | RESERVED | R | 0h | RESERVED |
REG1D_MASK 1 is shown in Table 9-38.
Return to the Summary Table.
MASK 1
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | BATOVP_MASK | R/W | 0h | Reset by: REG_RST | BATOVP Mask Type : R/W POR: 0b 0h = BATOVP flag produce INT 1h = BATOVP flag does not produce INT |
| 6 | BATOVP_ALM_MASK | R/W | 0h | Reset by: REG_RST | BATOVP_ALM Mask Type : R/W POR: 0b 0h = BATOVP_ALM flag produce INT 1h = BATOVP _ALM flag does not produce INT |
| 5 | VOUTOVP_MASK | R/W | 0h | Reset by: REG_RST | VOUTOVP Mask Type : R/W POR: 0b 0h = VOUTOVP flag produce INT 1h = VOUTOVP flag does not produce INT |
| 4 | BATOCP_MASK | R/W | 0h | Reset by: REG_RST | BATOCP Mask Type : R/W POR: 0b 0h = BATOCP flag produce INT 1h = BATOCP flag does not produce INT |
| 3 | BATOCP_ALM_MASK | R/W | 0h | Reset by: REG_RST | BATOCP_ALM Mask Type : R/W POR: 0b 0h = BATOCP_ALM flag produce INT 1h = BATOCP_ALM flag does not produce INT |
| 2 | BATUCP_ALM_MASK | R/W | 0h | Reset by: REG_RST | BATUCP_ALM Mask Type : R/W POR: 0b 0h = BATUCP_ALM flag produce INT 1h = BATUCP_ALM flag does not produce INT |
| 1 | BUSOVP_MASK | R/W | 0h | Reset by: REG_RST | BUSOVP Mask Type : R/W POR: 0b 0h = BUSOVP flag produce INT 1h = BUSOVP flag does not produce INT |
| 0 | BUSOVP_ALM_MASK | R/W | 0h | Reset by: REG_RST | BUSOVP_ALM Mask Type : R/W POR: 0b 0h = BUSOVP_ALM flag produce INT 1h = BUSOVP_ALM flag does not produce INT |
REG1E_MASK 2 is shown in Table 9-39.
Return to the Summary Table.
MASK 2
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 |
BUSOCP_MASK | R/W | 0h |
Reset by: REG_RST | BUSOCP Mask Type : R/W POR: 0b 0h = BUSOCP flag produce INT 1h = BUSOCP flag does not produce INT |
| 6 | BUSOCP_ALM_MASK | R/W | 0h | Reset by: REG_RST | BUSOCP_ALM Mask Type : R/W POR: 0b 0h = BUSOCP_ALM flag produce INT 1h = BUSOCP_ALM flag does not produce INT |
| 5 | BUSUCP_MASK | R/W | 0h | Reset by: REG_RST | BUSUCP Mask Type : R/W POR: 0b 0h = BUSUCP flag produce INT 1h = BUSUCP flag does not produce INT |
| 4 | BUSRCP_MASK | R/W | 0h | Reset by: REG_RST | BUSRCP Mask Type : R/W POR: 0b 0h = BUSRCP flag produce INT 1h = BUSRCP flag does not produce INT |
| 3 | RESERVED | R/W | 0h | Reset by: REG_RST | RESERVED |
| 2 | CFLY_SHORT_MASK | R/W | 0h | Reset by: REG_RST | CFLY_SHORT Mask Type : R/W POR: 0b 0h = CFLY_SHORT flag produce INT 1h = CFLY_SHORT flag does not produce INT |
| 1 | RESERVED | R/W | 0h | Reset by: REG_RST | RESERVED Type : R/W POR: 0h |
| 0 | RESERVED | R | 0h | RESERVED |
REG1F_MASK 3 is shown in Table 9-40.
Return to the Summary Table.
MASK 3
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | VAC1OVP_MASK | R/W | 0h | Reset by: REG_RST | VAC1OVP Mask Type : R/W POR: 0b 0h = VAC1OVP flag produce INT 1h = VAC1OVP flag does not produce INT |
| 6 | VAC2OVP_MASK | R/W | 0h | Reset by: REG_RST | VAC2OVP Mask Type : R/W POR: 0b 0h = VAC2OVP flag produce INT 1h = VAC2OVP flag does not produce INT |
| 5 | VOUTPRESENT_MASK | R/W | 0h | Reset by: REG_RST | VOUTPRESENT Mask Type : R/W POR: 0b 0h = VOUTPRESENT flag produce INT 1h = VOUTPRESENT flag does not produce INT |
| 4 | VAC1PRESENT_MASK | R/W | 0h | Reset by: REG_RST | VAC1PRESENT Mask Type : R/W POR: 0b 0h = VAC1PRESENT flag produce INT 1h = VAC1PRESENT flag does not produce INT |
| 3 | VAC2PRESENT_MASK | R/W | 0h | Reset by: REG_RST | VAC2PRESENT Mask Type : R/W POR: 0b 0h = VAC2PRESENT flag produce INT 1h = VAC2PRESENT flag does not produce INT |
| 2 | VBUSPRESENT_MASK | R/W | 0h | Reset by: REG_RST | VBUSPRESENT Mask Type : R/W POR: 0b 0h = VBUSPRESENT flag produce INT 1h = VBUSPRESENT flag does not produce INT |
| 1 | ACRB1_CONFIG_MASK | R/W | 0h | Reset by: REG_RST | ACFET1-RBFET1 CONFIG Mask Type : R/W POR: 0b 0h = ACRB1_CONFIG flag produce INT 1h = ACRB1_CONFIG flag does not produce INT |
| 0 | ACRB2_CONFIG_MASK | R/W | 0h | Reset by: REG_RST | ACFET2-RBFET2 CONFIG Mask Type : R/W POR: 0b 0h = ACRB2_CONFIG flag produce INT 1h = ACRB2_CONFIG flag does not produce INT |
REG20_MASK 4 is shown in Table 9-41.
Return to the Summary Table.
MASK 4
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | ADC_DONE_MASK | R/W | 0h | Reset by: REG_RST | ADC_DONE Mask Type : R/W POR: 0b 0h = ADC_DONE flag produce INT 1h = ADC_DONE flag does not produce INT |
| 6 | SS_TIMEOUT_MASK | R/W | 0h | Reset by: REG_RST | SS_TIMEOUT Mask Type : R/W POR: 0b 0h = SS_TIMEOUT flag produce INT 1h = SS_TIMEOUT flag does not produce INT |
| 5 | TSBUS_TSBAT_ALM_MASK | R/W | 0h | Reset by: REG_RST | TSBUS_TSBAT_ALM Mask Type : R/W POR: 0b 0h = TSBUS_TSBAT_ALM flag produce INT 1h = TSBUS_TSBAT_ALM flag does not produce INT |
| 4 | TSBUS_FLT_MASK | R/W | 0h | Reset by: REG_RST | TSBUS_FLT Mask Type : R/W POR: 0b 0h = TSBUS_FLT flag produce INT 1h = TSBUS_FLT flag does not produce INT |
| 3 | TSBAT_FLT_MASK | R/W | 0h | Reset by: REG_RST | TSBAT_FLT Mask Type : R/W POR: 0b 0h = TSBAT_FLT flag produce INT 1h = TSBAT_FLT flag does not produce INT |
| 2 | TDIE_FLT_MASK | R/W | 0h | Reset by: REG_RST | TDIE_FLT Mask Type : R/W POR: 0b 0h = TDIE_FLT flag produce INT 1h = TDIE_FLT flag does not produce INT |
| 1 | TDIE_ALM_MASK | R/W | 0h | Reset by: REG_RST | TDIE_ALM Mask Type : R/W POR: 0b 0h = TDIE_ALM flag produce INT 1h = TDIE_ALM flag does not produce INT |
| 0 | WD_MASK | R/W | 0h | Reset by: REG_RST | Watchdog Mask Type : R/W POR: 0b 0h = WD flag produce INT 1h = WD flag does not produce INT |
REG21_MASK 5 is shown in Table 9-42.
Return to the Summary Table.
MASK 5
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | REGN_GOOD_MASK | R/W | 0h | Reset by: REG_RST | REGN_GOOD Mask Type : R/W POR: 0b 0h = REGN_GOOD flag produce INT 1h = REGN_GOOD flag does not produce INT |
| 6 | CONV_ACTIVE_MASK | R/W | 0h | Reset by: REG_RST | CONV_ACTIVE Mask Type : R/W POR: 0b 0h = CONV_ACTIVE flag produce INT 1h = CONV_ACTIVE flag does not produce INT |
| 5 | RESERVED | R/W | 0h | Reset by: REG_RST | RESERVED Type : R/W POR: 0h |
| 4 | VBUS_ERRHI_MASK | R/W | 0h | Reset by: REG_RST | VBUS_ERRHI Mask Type : R/W POR: 0b 0h = VBUS_ERRHI flag produce INT 1h = VBUS_ERRHI flag does not produce INT |
| 3-0 | RESERVED | R | 0h | RESERVED |
REG22_DEVICE_INFO is shown in Table 9-43.
Return to the Summary Table.
DEVICE INFO
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | DEVICE_REV_3:0 | R | 0h | Device Revision Type : R POR: 0h |
| 3-0 | DEVICE_ID_3:0 | R | 0h | Device ID Type : R POR: 0h |
REG23_ADC_CONTROL 1 is shown in Table 9-44.
Return to the Summary Table.
ADC_CONTROL 1
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | ADC_EN | R/W | 0h | Reset by: WATCHDOG REG_RST | ADC Enable Type : R/W POR: 0b 0h = Disable 1h = Enable |
| 6 | ADC_RATE | R/W | 0h | Reset by: REG_RST | ADC Rate Type : R/W POR: 0b 0h = Continuous conversion 1h = 1 shot |
| 5 | ADC_AVG | R/W | 0h | Reset by: REG_RST | ADC Average Type : R/W POR: 0b 0h = Single value 1h = Running average |
| 4 | ADC_AVG_INIT | R/W | 0h | Reset by: REG_RST | ADC Average Initial Value Type : R/W POR: 0b 0h = Start average using the existing register value 1h = Start average using a new conversion |
| 3-2 | ADC_SAMPLE_1:0 | R/W | 0h | Reset by: REG_RST | ADC Sample Speed Type : R/W POR: 00b 0h = 15 bit 1h = 14 bit 2h = 13 bit 3h = 11 bit |
| 1 | IBUS_ADC_DIS | R/W | 0h | Reset by: REG_RST | IBUS ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 0 | VBUS_ADC_DIS | R/W | 0h | Reset by: REG_RST | VBUS ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
REG24_ADC_CONTROL 2 is shown in Table 9-45.
Return to the Summary Table.
ADC_CONTROL 2
| Bit | Field | Type | Reset | Note | Description |
|---|---|---|---|---|---|
| 7 | VAC1_ADC_DIS | R/W | 0h | Reset by: REG_RST | VAC1 ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 6 | VAC2_ADC_DIS | R/W | 0h | Reset by: REG_RST | VAC2 ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 5 | VOUT_ADC_DIS | R/W | 0h | Reset by: REG_RST | VOUT ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 4 | VBAT_ADC_DIS | R/W | 0h | Reset by: REG_RST | VBAT ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 3 | IBAT_ADC_DIS | R/W | 0h | Reset by: REG_RST | IBAT ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 2 | TSBUS_ADC_DIS | R/W | 0h | Reset by: REG_RST | TSBUS ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 1 | TSBAT_ADC_DIS | R/W | 0h | Reset by: REG_RST | TSBAT ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
| 0 | TDIE_ADC_DIS | R/W | 0h | Reset by: REG_RST | TDIE ADC Control Type : R/W POR: 0b 0h = Enable 1h = Disable |
REG25_IBUS_ADC is shown in Table 9-46.
Return to the Summary Table.
IBUS_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | IBUS_ADC_15:0 | R | 0h | IBUS ADC Reading Type : R POR: 0 mA (0h) Range : 0 mA - 7000 mA Switched Cap Mode: Fixed Offset : 66 mA Bit Step Size : 0.9972 mA Bypass Mode: Fixed Offset : 64 mA Bit Step Size : 1.0279 mA |
REG27_VBUS_ADC is shown in Table 9-47.
Return to the Summary Table.
VBUS_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | VBUS_ADC_15:0 | R | 0h | VBUS ADC Reading Type : R POR: 0 mV (0h) Range : 0 mV - 16385 mV Fixed Offset : 0 mV Bit Step Size : 1.002 mV |
REG29_VAC1_ADC is shown in Table 9-48.
Return to the Summary Table.
VAC1_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | VAC1_ADC_15:0 | R | 0h | VAC1 ADC Reading Type : R POR: 0 mV (0h) Range : 0 mV - 14000 mV Fixed Offset : 3 mV Bit Step Size : 1.0008 mV |
REG2B_VAC2_ADC is shown in Table 9-49.
Return to the Summary Table.
VAC2_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | VAC2_ADC_15:0 | R | 0h | VAC2 ADC Reading Type : R POR: 0 mV (0h) Range : 0 mV - 14000 mV Fixed Offset : 5 mV Bit Step Size : 1.0006 mV |
REG2D_VOUT_ADC is shown in Table 9-50.
Return to the Summary Table.
VOUT_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | VOUT_ADC_15:0 | R | 0h | VOUT ADC Reading Type : R POR: 0 mV (0h) Range : 0 mV - 6000 mV Fixed Offset : 2 mV Bit Step Size : 1.0037 mV |
REG2F_VBAT_ADC is shown in Table 9-51.
Return to the Summary Table.
VBAT_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | VBAT_ADC_15:0 | R | 0h | VBAT ADC Reading Type : R POR: 0 mV (0h) Range : 0 mV - 6000 mV Fixed Offset : 1 mV Bit Step Size : 1.017 mV |
REG31_IBAT_ADC is shown in Table 9-52.
Return to the Summary Table.
IBAT_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | IBAT_ADC_15:0 | R | 0h | IBAT ADC Reading Type : R POR: 0 mA (0h) Range : 0 mA - 12000 mA Fixed Offset : -150 mA Bit Step Size : 0.999 mA |
REG33_TSBUS_ADC is shown in Table 9-53.
Return to the Summary Table.
TSBUS_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | TSBUS_ADC_15:0 | R | 0h | TSBUS ADC Reading Type : R POR: 0% (0h) Range : 0% - 50% Fixed Offset : 0.1% Bit Step Size : 0.09860% |
REG35_TSBAT_ADC is shown in Table 9-54.
Return to the Summary Table.
TSBAT_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | TSBAT_ADC_15:0 | R | 0h | TSBAT ADC Reading Type : R POR: 0% (0h) Range : 0% - 50% Fixed Offset : 0.065% Bit Step Size : 0.09762% |
REG37_TDIE_ADC is shown in Table 9-55.
Return to the Summary Table.
TDIE_ADC
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15-0 | TDIE_ADC_15:0 | R | 0h | TDIE ADC Reading Type : R POR: 0°C (0h) Range : -40°C - 150°C Fixed Offset : -3.5°C Bit Step Size : 0.5079°C |