ZHCSGM5A August   2017  – November 2017 TLV320AIC3109-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化图表
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Audio Data Serial Interface Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hardware Reset
      2. 7.3.2  Digital Audio Data Serial Interface
        1. 7.3.2.1 Right-Justified Mode
        2. 7.3.2.2 Left-Justified Mode
        3. 7.3.2.3 I2S Mode
        4. 7.3.2.4 DSP Mode
        5. 7.3.2.5 TDM Data Transfer
      3. 7.3.3  Audio Data Converters
        1. 7.3.3.1 Audio Clock Generation
        2. 7.3.3.2 Mono Audio ADC
          1. 7.3.3.2.1 Mono Audio ADC High-Pass Filter
          2. 7.3.3.2.2 Automatic Gain Control (AGC)
            1. 7.3.3.2.2.1 Target Level
            2. 7.3.3.2.2.2 Attack Time
            3. 7.3.3.2.2.3 Decay Time
            4. 7.3.3.2.2.4 Noise Gate Threshold
            5. 7.3.3.2.2.5 Maximum PGA Gain Applicable
      4. 7.3.4  Mono Audio DAC
        1. 7.3.4.1 Digital Audio Processing for Playback
        2. 7.3.4.2 Digital Interpolation Filter
        3. 7.3.4.3 Delta-Sigma Audio DAC
        4. 7.3.4.4 Audio DAC Digital Volume Control
        5. 7.3.4.5 Increasing DAC Dynamic Range
        6. 7.3.4.6 Analog Output Common-mode Adjustment
      5. 7.3.5  Audio Analog Inputs
      6. 7.3.6  Analog Fully Differential Line Output Drivers
      7. 7.3.7  Analog High-Power Output Drivers
      8. 7.3.8  Output Stage Volume Controls
      9. 7.3.9  Input Impedance and VCM Control
      10. 7.3.10 MICBIAS Generation
      11. 7.3.11 Short-Circuit Output Protection
      12. 7.3.12 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Path Mode
        1. 7.4.1.1 ADC PGA Signal Bypass Path Functionality
        2. 7.4.1.2 Passive Analog Bypass During Power Down
      2. 7.4.2 Digital Audio Processing for Record Path
    5. 7.5 Programming
      1. 7.5.1 I2C Control Interface
        1. 7.5.1.1 I2C Bus Debug in a Glitched System
    6. 7.6 Register Maps
      1. 7.6.1 Register Map Structure
      2. 7.6.2 Page 0 Registers
        1. 7.6.2.1  Register 0: Page Select (address = 0h) [reset = 0000 0000], Page 0
          1. Table 9. Register 0 Field Descriptions
        2. 7.6.2.2  Register 1: Software Reset Register (address = 1h) [reset = 0000 0000], Page 0
          1. Table 10. Register 1 Field Descriptions
        3. 7.6.2.3  Register 2: Codec Sample Rate Select Register (address = 2h) [reset = 0000 0000], Page 0
          1. Table 11. Register 2 Field Descriptions
        4. 7.6.2.4  Register 3: PLL Programming Register A (address = 3h) [reset = 0001 0000], Page 0
          1. Table 12. Register 3 Field Descriptions
        5. 7.6.2.5  Register 4: PLL Programming Register B (address = 4h) [reset = 0000 0100]
          1. Table 13. Register 4 Field Descriptions
        6. 7.6.2.6  Register 5: PLL Programming Register C (address = 5h) [reset = 0000 0000], Page 0
          1. Table 14. Register 5 Field Descriptions
        7. 7.6.2.7  Register 6: PLL Programming Register D (address = 6h) [reset = 0000 0000]
          1. Table 15. Register 6 Field Descriptions
        8. 7.6.2.8  Register 7: Codec Data-Path Setup Register (address = 7h) [reset = 0000 0000], Page 0
          1. Table 16. Register 7 Field Descriptions
        9. 7.6.2.9  Register 8: Audio Serial Data Interface Control Register A (address = 8h) [reset = 0000 0000], Page 0
          1. Table 17. Register 8 Field Descriptions
        10. 7.6.2.10 Register 9: Audio Serial Data Interface Control Register B (address = 9h) [reset = 0000 0000], Page 0
          1. Table 18. Register 9 Field Descriptions
        11. 7.6.2.11 Register 10: Audio Serial Data Interface Control Register C (address = Ah) [reset = 0000 0000], Page 0
          1. Table 19. Register 10 Field Descriptions
        12. 7.6.2.12 Register 11: Audio Codec Overflow Flag Register (address = Bh) [reset = 0000 0001], Page 0
          1. Table 20. Register 11 Field Descriptions
        13. 7.6.2.13 Register 12: Audio Codec Digital Filter Control Register (address = Ch) [reset = 0000 0000], Page 0
          1. Table 21. Register 12 Field Descriptions
        14. 7.6.2.14 Register 13: Headset/Button Press Detection Register A (address = Dh) [reset = 0000 0000], Page 0
          1. Table 22. Register 13 Field Descriptions
        15. 7.6.2.15 Register 14: Headset/Button Press Detection Register B (address = Eh) [reset = 0000 0000], Page 0
          1. Table 23. Register 14 Field Descriptions
        16. 7.6.2.16 Register 15: ADC PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
          1. Table 24. Register 15 Field Descriptions
        17. 7.6.2.17 Register 16: Auxiliary PGA Gain Control Register (address = Fh) [reset = 1000 0000], Page 0
          1. Table 25. Register 16 Field Descriptions
        18. 7.6.2.18 Register 17–18: Reserved (address = 11h–12h) [reset = 1111 1111], Page 0
          1. Table 26. Register 17 Field Descriptions
        19. 7.6.2.19 Register 19: MIC1P/LINE1P to ADC Control Register (address = 13h) [reset = 0111 1000], Page 0
          1. Table 27. Register 19 Field Descriptions
        20. 7.6.2.20 Register 20: Reserved (address = 14h) [reset = 0111 1000], Page 0
          1. Table 28. Register 20 Field Descriptions
        21. 7.6.2.21 Register 21: MIC2P/LINE2P to ADC Control Register (address = 15h) [reset = 0111 1000], Page 0
          1. Table 29. Register 21 Field Descriptions
        22. 7.6.2.22 Registers 22–24: Reserved (address = 16h–18h) [reset = 0111 1000], Page 0
          1. Table 30. Register 22 Field Descriptions
        23. 7.6.2.23 Register 25: MICBIAS Control Register (address = 25h) [reset = 0000 0110], Page 0
          1. Table 31. Register 25 Field Descriptions
        24. 7.6.2.24 Register 26: AGC Control Register A (address = 1Ah) [reset = 0000 0000], Page 0
          1. Table 32. Register 26 Field Descriptions
        25. 7.6.2.25 Register 27: AGC Control Register B (address = 1Bh) [reset = 1111 1110], Page 0
          1. Table 33. Register 27 Field Descriptions
        26. 7.6.2.26 Register 28: AGC Control Register C (address = 1Ch) [reset = 0000 0000], Page 0
          1. Table 34. Register 28 Field Descriptions
        27. 7.6.2.27 Register 29: Reserved (address = 1Dh) [reset = 0000 0000], Page 0
          1. Table 35. Register 29 Field Descriptions
        28. 7.6.2.28 Register 30: Reserved (address = 1Eh) [reset = 1111 1110], Page 0
          1. Table 36. Register 30 Field Descriptions
        29. 7.6.2.29 Register 31: Reserved (address = 1Fh) [reset = 0000 0000], Page 0
          1. Table 37. Register 31 Field Descriptions
        30. 7.6.2.30 Register 32: AGC Gain Register (address = 20h) [reset = 1000 0000], Page 0
          1. Table 38. Register 32 Field Descriptions
        31. 7.6.2.31 Register 33: Reserved (address = 21h) [reset = 0000 0000], Page 0
          1. Table 39. Register 33 Field Descriptions
        32. 7.6.2.32 Register 34: AGC Noise Gate Debounce Register (address = 22h) [reset = 0000 0000], Page 0
          1. Table 40. Register 34 Field Descriptions
        33. 7.6.2.33 Register 35: Reserved (address = 23h) [reset = 0000 0000], Page 0
          1. Table 41. Register 35 Field Descriptions
        34. 7.6.2.34 Register 36: ADC Flag Register (address = 24h) [reset = 0000 0000], Page 0
          1. Table 42. Register 36 Field Descriptions
        35. 7.6.2.35 Register 37: DAC Power and Output Driver Control Register (address = 25h) [reset = 0000 0000], Page 0
          1. Table 43. Register 37 Field Descriptions
        36. 7.6.2.36 Register 38: High-Power Output Driver Control Register (address = 26h) [reset = 0000 0000], Page 0
          1. Table 44. Register 38 Field Descriptions
        37. 7.6.2.37 Register 39: Reserved (address = 27h) [reset = 0000 0000], Page 0
          1. Table 45. Register 39 Field Descriptions
        38. 7.6.2.38 Register 40: High-Power Output Stage Control Register (address = 28h) [reset = 0000 0000], Page 0
          1. Table 46. Register 40 Field Descriptions
        39. 7.6.2.39 Register 41: DAC Output Switching Control Register (address = 29h) [reset = 0000 0000], Page 0
          1. Table 47. Register 41 Field Descriptions
        40. 7.6.2.40 Register 42: Output Driver Pop Reduction Register (address = 2Ah) [reset = 0000 0000], Page 0
          1. Table 48. Register 42 Field Descriptions
        41. 7.6.2.41 Register 43: DAC Digital Volume Control Register (address = 2Bh) [reset = 1000 0000], Page 0
          1. Table 49. Register 43 Field Descriptions
        42. 7.6.2.42 Register 44: Reserved (address = 2Ch) [reset = 1000 0000], Page 0
          1. Table 50. Register 44 Field Descriptions
        43. 7.6.2.43 Registers 45–50: Reserved (address = 2Dh–32h) [reset = 0000 0000], Page 0
          1. Table 51. Register 45 Field Descriptions
        44. 7.6.2.44 Register 51: Reserved (address = 33h) [reset = 0000 0100], Page 0
          1. Table 52. Register 51 Field Descriptions
        45. 7.6.2.45 Registers 52–57: Reserved (address = 34h–39h) [reset = 0000 0000], Page 0
          1. Table 53. Register 52 Field Descriptions
        46. 7.6.2.46 Register 58: Reserved (address = 3Ah) [reset = 0000 0100], Page 0
          1. Table 54. Register 58 Field Descriptions
        47. 7.6.2.47 Register 59: Reserved (address = 3Bh) [reset = 0000 0000], Page 0
          1. Table 55. Register 59 Field Descriptions
        48. 7.6.2.48 Register 60: PGA to HPOUT Volume Control Register (address = 3Ch) [reset = 0000 0000], Page 0
          1. Table 56. Register 60 Field Descriptions
        49. 7.6.2.49 Register 61: DAC_1 to HPOUT Volume Control Register (address = 3Dh) [reset = 0000 0000], Page 0
          1. Table 57. Register 61 Field Descriptions
        50. 7.6.2.50 Register 62: Reserved Register (address = 3Eh) [reset = 0000 0000], Page 0
          1. Table 58. Register 62 Field Descriptions
        51. 7.6.2.51 Register 63: PGA_AUX to HPOUT Volume Control Register (address = 3Fh) [reset = 0000 0000], Page 0
          1. Table 59. Register 63 Field Descriptions
        52. 7.6.2.52 Register 64: Reserved (address = 40h) [reset = 0000 0000], Page 0
          1. Table 60. Register 64 Field Descriptions
        53. 7.6.2.53 Register 65: HPOUT Output Level Control Register (address = 41h) [reset = 0000 0100], Page 0
          1. Table 61. Register 65 Field Descriptions
        54. 7.6.2.54 Register 66: Reserved (address = 42h) [reset = 0000 0000], Page 0
          1. Table 62. Register 66 Field Descriptions
        55. 7.6.2.55 Register 67: PGA to HPCOM Volume Control Register (address = 43h) [reset = 0000 0000], Page 0
          1. Table 63. Register 67 Field Descriptions
        56. 7.6.2.56 Register 68: DAC_1 to HPCOM Volume Control Register (address = 44h) [reset = 0000 0000], Page 0
          1. Table 64. Register 68 Field Descriptions
        57. 7.6.2.57 Register 69: Reserved (address = 45h) [reset = 0000 0000], Page 0
          1. Table 65. Register 69 Field Descriptions
        58. 7.6.2.58 Register 70: PGA_AUX to HPCOM Volume Control Register (address = 46h) [reset = 0000 0000], Page 0
          1. Table 66. Register 70 Field Descriptions
        59. 7.6.2.59 Register 71: Reserved (address = 47h) [reset = 0000 0000], Page 0
          1. Table 67. Register 71 Field Descriptions
        60. 7.6.2.60 Register 72: HPCOM Output Level Control Register (address = 48h) [reset = 0000 0100], Page 0
          1. Table 68. Register 72 Field Descriptions
        61. 7.6.2.61 Registers 73–80: Reserved (address = 49h–50h) [reset = 0000 0000], Page 0
          1. Table 69. Registers 73–80 Field Descriptions
        62. 7.6.2.62 Register 81: PGA to LEFT_LOP/M Volume Control Register (address = 51h) [reset = 0000 0000], Page 0
          1. Table 70. Register 81 Field Descriptions
        63. 7.6.2.63 Register 82: DAC_1 to LEFT_LOP/M Volume Control Register (address = 52h) [reset = 0000 0000], Page 0
          1. Table 71. Register 82 Field Descriptions
        64. 7.6.2.64 Register 83: Reserved (address = 53h) [reset = 0000 0000], Page 0
          1. Table 72. Register 83 Field Descriptions
        65. 7.6.2.65 Register 84: PGA_AUX to LEFT_LOP/M Volume Control Register (address = 54h) [reset = 0000 0000], Page 0
          1. Table 73. Register 84 Field Descriptions
        66. 7.6.2.66 Register 85: Reserved (address = 55h) [reset = 0000 0000], Page 0
          1. Table 74. Register 85 Field Descriptions
        67. 7.6.2.67 Register 86: LEFT_LOP/M Output Level Control Register (address = 56h) [reset = 0000 0000], Page 0
          1. Table 75. Register 86 Field Descriptions
        68. 7.6.2.68 Register 87: Reserved (address = 57h) [reset = 0000 0000], Page 0
          1. Table 76. Register 87 Field Descriptions
        69. 7.6.2.69 Register 88: PGA to RIGHT_LOP/M Volume Control (address = 58h) [reset = 0000 0000], Page 0
          1. Table 77. Register 88 Field Descriptions
        70. 7.6.2.70 Register 89: DAC_1 to RIGHT_LOP/M Volume Control (address = 59h) [reset = 0000 0000], Page 0
          1. Table 78. Register 89 Field Descriptions
        71. 7.6.2.71 Register 90: Reserved (address = 5A) [reset = 0000 0000], Page 0
          1. Table 79. Register 90 Field Descriptions
        72. 7.6.2.72 Register 91: PGA_AUX to RIGHT_LOP/M Volume Control (address = 5Bh) [reset = 0000 0000], Page 0
          1. Table 80. Register 91 Field Descriptions
        73. 7.6.2.73 Register 92: Reserved (address = 5Ch) [reset = 0000 0000], Page 0
          1. Table 81. Register 92 Field Descriptions
        74. 7.6.2.74 Register 93: RIGHT_LOP/M Output Level Control (address = 5Dh) [reset = 0000 0000], Page 0
          1. Table 82. Register 93 Field Descriptions
        75. 7.6.2.75 Register 94: Module Power Status Register (address = 5Eh) [reset = 0000 0000], Page 0
          1. Table 83. Register 94 Field Descriptions
        76. 7.6.2.76 Register 95: Output Driver Short-Circuit Detection Status Register (address = 5Fh) [reset = 0000 0000], Page 0
          1. Table 84. Register 95 Field Descriptions
        77. 7.6.2.77 Register 96: Sticky Interrupt Flags Register (address = 60h) [reset = 0000 0000], Page 0
          1. Table 85. Register 96 Field Descriptions
        78. 7.6.2.78 Register 97: Real-Time Interrupt Flags Register (address = 61h) [reset = 0000 0000], Page 0
          1. Table 86. Register 97 Field Descriptions
        79. 7.6.2.79 Registers 98–100: Reserved (address = 62h–64h) [reset = 0000 0000], Page 0
          1. Table 87. Registers 98–100 Field Descriptions
        80. 7.6.2.80 Register 101: Clock Register (address = 65h) [reset = 0000 0000], Page 0
          1. Table 88. Register 101 Field Descriptions
        81. 7.6.2.81 Register 102: Clock Generation Control Register (address = 66h) [reset = 0000 0000], Page 0
          1. Table 89. Register 102 Field Descriptions
        82. 7.6.2.82 Register 103: AGC New Programmable Attack Time Register (address = 67h) [reset = 0000 0000], Page 0
          1. Table 90. Register 103 Field Descriptions
        83. 7.6.2.83 Register 104: AGC New Programmable Decay Time Register (address = 68h) [reset = 0000 0000], Page 0
          1. Table 91. Register 104 Field Descriptions
        84. 7.6.2.84 Registers 105–106: Reserved (address = 69h–6Ah) [reset = 0000 0000], Page 0
          1. Table 92. Register 105 Field Descriptions
        85. 7.6.2.85 Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register (address = 6Bh) [reset = 0000 0000], Page 0
          1. Table 93. Register 107 Field Descriptions
        86. 7.6.2.86 Register 108: Passive Analog Signal Bypass Selection During Power Down Register (address = 6Ch) [reset = 0000 0000], Page 0
          1. Table 94. Register 108 Field Descriptions
        87. 7.6.2.87 Register 109: DAC Quiescent Current Adjustment Register (address = 6Dh) [reset = 0000 0000], Page 0
          1. Table 95. Register 109 Field Descriptions
        88. 7.6.2.88 Registers 110–127: Reserved (address = 6Eh–7Fh) [reset = 0000 0000], Page 0
          1. Table 96. Registers 110–127 Field Descriptions
      3. 7.6.3 Page 1 Register Descriptions
        1. 7.6.3.1  Register 0: Page Select Register (address = 0h) [reset = 0000 0000], Page 1
          1. Table 97. Register 0 Field Descriptions
        2. 7.6.3.2  Register 1: Audio Effects Filter N0 Coefficient MSB Register (address = 1h) [reset = 0110 1011], Page 1
          1. Table 98. Register 1 Field Descriptions
        3. 7.6.3.3  Register 2: Audio Effects Filter N0 Coefficient LSB Register (address = 2h) [reset = 1110 0011], Page 1
          1. Table 99. Register 2 Field Descriptions
        4. 7.6.3.4  Register 3: Audio Effects Filter N1 Coefficient MSB Register (address = 3h) [reset = 1001 0110], Page 1
          1. Table 100. Register 3 Field Descriptions
        5. 7.6.3.5  Register 4: Audio Effects Filter N1 Coefficient LSB Register (address = 4h) [reset = 0110 0110], Page 1
          1. Table 101. Register 4 Field Descriptions
        6. 7.6.3.6  Register 5: Audio Effects Filter N2 Coefficient MSB Register (address = 5h) [reset = 0110 0111], Page 1
          1. Table 102. Register 5 Field Descriptions
        7. 7.6.3.7  Register 6: Audio Effects Filter N2 Coefficient LSB Register (address = 6h) [reset = 0101 1101], Page 1
          1. Table 103. Register 6 Field Descriptions
        8. 7.6.3.8  Register 7: Audio Effects Filter N3 Coefficient MSB Register (address = 7h) [reset = 0110 1011], Page 1
          1. Table 104. Register 7 Field Descriptions
        9. 7.6.3.9  Register 8: Audio Effects Filter N3 Coefficient LSB Register (address = 8h) [reset = 1110 0011], Page 1
          1. Table 105. Register 8 Field Descriptions
        10. 7.6.3.10 Register 9: Audio Effects Filter N4 Coefficient MSB Register (address = 9h) [reset = 1001 0110], Page 1
          1. Table 106. Register 9 Field Descriptions
        11. 7.6.3.11 Register 10: Audio Effects Filter N4 Coefficient LSB Register (address = Ah) [reset = 0110 0110], Page 1
          1. Table 107. Register 10 Field Descriptions
        12. 7.6.3.12 Register 11: Audio Effects Filter N5 Coefficient MSB Register (address = Bh) [reset = 0110 0111], Page 1
          1. Table 108. Register 11 Field Descriptions
        13. 7.6.3.13 Register 12: Audio Effects Filter N5 Coefficient LSB Register (address = Ch) [reset = 0101 1101], Page 1
          1. Table 109. Register 12 Field Descriptions
        14. 7.6.3.14 Register 13: Audio Effects Filter D1 Coefficient MSB Register (address = Dh) [reset = 0111 1101], Page 1
          1. Table 110. Register 13 Field Descriptions
        15. 7.6.3.15 Register 14: Audio Effects Filter D1 Coefficient LSB Register (address = Eh) [reset = 1000 0011h], Page 1
          1. Table 111. Register 14 Field Descriptions
        16. 7.6.3.16 Register 15: Audio Effects Filter D2 Coefficient MSB Register (address = Fh) [reset = 1000 0100], Page 1
          1. Table 112. Register 15 Field Descriptions
        17. 7.6.3.17 Register 16: Audio Effects Filter D2 Coefficient LSB Register (address = 10h) [reset = 1110 1110], Page 1
          1. Table 113. Register 16 Field Descriptions
        18. 7.6.3.18 Register 17: Audio Effects Filter D4 Coefficient MSB Register (address = 11h) [reset = 0111 1101], Page 1
          1. Table 114. Register 17 Field Descriptions
        19. 7.6.3.19 Register 18: Audio Effects Filter D4 Coefficient LSB Register (address = 12h) [reset = 1000 0011], Page 1
          1. Table 115. Register 18 Field Descriptions
        20. 7.6.3.20 Register 19: Audio Effects Filter D5 Coefficient MSB Register (address = 13h) [reset = 1000 0100], Page 1
          1. Table 116. Register 19 Field Descriptions
        21. 7.6.3.21 Register 20: Audio Effects Filter D5 Coefficient LSB Register (address = 14h) [reset = 1110 1110], Page 1
          1. Table 117. Register 20 Field Descriptions
        22. 7.6.3.22 Register 21: De-Emphasis Filter N0 Coefficient MSB Register (address = 15h) [reset = 0011 1001], Page 1
          1. Table 118. Register 21 Field Descriptions
        23. 7.6.3.23 Register 22: De-Emphasis Filter N0 Coefficient LSB Register (address = 16h) [reset = 0101 0101], Page 1
          1. Table 119. Register 22 Field Descriptions
        24. 7.6.3.24 Register 23: De-Emphasis Filter N1 Coefficient MSB Register (address = 17h) [reset = 1111 0011], Page 1
          1. Table 120. Register 23 Field Descriptions
        25. 7.6.3.25 Register 24: De-Emphasis Filter N1 Coefficient LSB Register (address = 18h) [reset = 0010 1101], Page 1
          1. Table 121. Register 24 Field Descriptions
        26. 7.6.3.26 Register 25: De-Emphasis Filter D1 Coefficient MSB Register (address = 19h) [reset = 0101 0011], Page 1
          1. Table 122. Register 25 Field Descriptions
        27. 7.6.3.27 Register 26: De-Emphasis Filter D1 Coefficient LSB Register (address = 1Ah) [reset = 0111 1110], Page 1
          1. Table 123. Register 26 Field Descriptions
        28. 7.6.3.28 Register 27: Reserved (address = 1Bh) [reset = 0110 1011], Page 1
          1. Table 124. Register 27 Field Descriptions
        29. 7.6.3.29 Register 28: Reserved (address = 1Ch) [reset = 1110 0011], Page 1
          1. Table 125. Register 28 Field Descriptions
        30. 7.6.3.30 Register 29: Reserved (address = 1Dh) [reset = 1001 0110], Page 1
          1. Table 126. Register 29 Field Descriptions
        31. 7.6.3.31 Register 30: Reserved (address = 1Eh) [reset = 0110 0110], Page 1
          1. Table 127. Register 30 Field Descriptions
        32. 7.6.3.32 Register 31: Reserved (address = 1Fh) [reset = 0110 0111], Page 1
          1. Table 128. Register 31 Field Descriptions
        33. 7.6.3.33 Register 32: Reserved (address = 20h) [reset = 0101 1101], Page 1
          1. Table 129. Register 32 Field Descriptions
        34. 7.6.3.34 Register 33: Reserved (address = 21h) [reset = 0110 1011], Page 1
          1. Table 130. Register 33 Field Descriptions
        35. 7.6.3.35 Register 34: Reserved (address = 22h) [reset = 1110 0011], Page 1
          1. Table 131. Register 34 Field Descriptions
        36. 7.6.3.36 Register 35: Reserved (address = 23h) [reset = 1001 0110], Page 1
          1. Table 132. Register 35 Field Descriptions
        37. 7.6.3.37 Register 36: Reserved (address = 24h) [reset = 0110 0110], Page 1
          1. Table 133. Register 36 Field Descriptions
        38. 7.6.3.38 Register 37: Reserved (address = 25h) [reset = 0110 0111], Page 1
          1. Table 134. Register 37 Field Descriptions
        39. 7.6.3.39 Register 38: Reserved (address = 26h) [reset = 0101 1101], Page 1
          1. Table 135. Register 38 Field Descriptions
        40. 7.6.3.40 Register 39: Reserved (address = 27h) [reset = 0111 1101], Page 1
          1. Table 136. Register 39 Field Descriptions
        41. 7.6.3.41 Register 40: Reserved (address = 28h) [reset = 1000 0011], Page 1
          1. Table 137. Register 40 Field Descriptions
        42. 7.6.3.42 Register 41: Reserved (address = 29h) [reset = 1000 0100], Page 1
          1. Table 138. Register 41 Field Descriptions
        43. 7.6.3.43 Register 42: Reserved (address = 2Ah) [reset = 1110 1110], Page 1
          1. Table 139. Register 42 Field Descriptions
        44. 7.6.3.44 Register 43: Reserved (address = 2Bh) [reset = 0111 1101], Page 1
          1. Table 140. Register 43 Field Descriptions
        45. 7.6.3.45 Register 44: Reserved (address = 2Ch) [reset = 1000 0011], Page 1
          1. Table 141. Register 44 Field Descriptions
        46. 7.6.3.46 Register 45: Reserved (address = 2Dh) [reset = 1000 0100], Page 1
          1. Table 142. Register 45 Field Descriptions
        47. 7.6.3.47 Register 46: Reserved (address = 2Eh) [reset = 1110 1110], Page 1
          1. Table 143. Register 46 Field Descriptions
        48. 7.6.3.48 Register 47: Reserved (address = 2Fh) [reset = 0011 1001], Page 1
          1. Table 144. Register 47 Field Descriptions
        49. 7.6.3.49 Register 48: Reserved (address = 30h) [reset = 0101 0101], Page 1
          1. Table 145. Register 48 Field Descriptions
        50. 7.6.3.50 Register 49: Reserved (address = 31h) [reset = 1111 0011], Page 1
          1. Table 146. Register 49 Field Descriptions
        51. 7.6.3.51 Register 50: Reserved (address = 32h) [reset = 0010 1101], Page 1
          1. Table 147. Register 50 Field Descriptions
        52. 7.6.3.52 Register 51: Reserved (address = 33h) [reset = 0101 0011], Page 1
          1. Table 148. Register 51 Field Descriptions
        53. 7.6.3.53 Register 52: Reserved (address = 34h) [reset = 0111 1110], Page 1
          1. Table 149. Register 52 Field Descriptions
        54. 7.6.3.54 Register 53: Reserved (address = 35h) [reset = 0111 1111], Page 1
          1. Table 150. Register 53 Field Descriptions
        55. 7.6.3.55 Register 54: Reserved (address = 36h) [reset = 1111 1111], Page 1
          1. Table 151. Register 54 Field Descriptions
        56. 7.6.3.56 Registers 55–64: Reserved (address = 37h–40h) [reset = 0000 0000], Page 1
          1. Table 152. Registers 55–64 Field Descriptions
        57. 7.6.3.57 Register 65: ADC High-Pass Filter N0 Coefficient MSB Register (address = 41h) [reset = 0011 1001], Page 1
          1. Table 153. Register 65 Field Descriptions
        58. 7.6.3.58 Register 66: ADC High-Pass Filter N0 Coefficient LSB Register (address = 42h) [reset = 1110 1010], Page 1
          1. Table 154. Register 66 Field Descriptions
        59. 7.6.3.59 Register 67: Channel ADC High-Pass Filter N1 Coefficient MSB Register (address = 43h) [reset = 1000 0000 , Page 1
          1. Table 155. Register 67 Field Descriptions
        60. 7.6.3.60 Register 68: Channel ADC High-Pass Filter N1 Coefficient LSB Register (address = 44h) [reset = 0001 0110], Page 1
          1. Table 156. Register 68 Field Descriptions
        61. 7.6.3.61 Register 69: Channel ADC High-Pass Filter D1 Coefficient MSB Register (address = 45h) [reset = 0111 1111], Page 1
          1. Table 157. Register 69 Field Descriptions
        62. 7.6.3.62 Register 70: Channel ADC High-Pass Filter D1 Coefficient LSB Register (address = 46h) [reset = 1101 0101], Page 1
          1. Table 158. Register 70 Field Descriptions
        63. 7.6.3.63 Register 71: Reserved (address = 47h) [reset = 0111 1111], Page 1
          1. Table 159. Register 71 Field Descriptions
        64. 7.6.3.64 Register 72: Reserved (address = 48h) [reset = 1110 1010], Page 1
          1. Table 160. Register 72 Field Descriptions
        65. 7.6.3.65 Register 73: Reserved (address = 49h) [reset = 1000 0000], Page 1
          1. Table 161. Register 73 Field Descriptions
        66. 7.6.3.66 Register 74: Reserved (address = 4Ah) [reset = 0001 0110], Page 1
          1. Table 162. Register 74 Field Descriptions
        67. 7.6.3.67 Register 75: Reserved (address = 4Bh) [reset = 0111 1111], Page 1
          1. Table 163. Register 75 Field Descriptions
        68. 7.6.3.68 Register 76: Reserved (address = 4Ch) [reset = 1101 0101], Page 1
          1. Table 164. Register 76 Field Descriptions
        69. 7.6.3.69 Registers 77h–127h: Reserved (address = 4Dh) [reset = 0000 0000], Page 1
          1. Table 165. Registers 77h–127h Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5.1 I2C Control Interface

The TLV320AIC3109-Q1 supports the I2C control protocol using 7-bit addressing and is capable of both standard and fast modes. As illustrated in Figure 28, the minimum timing for each tHD-STA, tSU-STA, and tSU-STO is 0.9 μs for I2C fast mode. The TLV320AIC3109-Q1 responds to the I2C address of 001 1000. I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors so the bus wires are high when not being driven low by a device. This way two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

TLV320AIC3109-Q1 t0114-02_las509.gifFigure 28. I2C Interface Timing

Communication on the I2C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the TLV320AIC3109-Q1 can only act as a slave device.

An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level when SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). When the SDA line settles, the SCL line is brought high then low. This pulse on SCL clocks the SDA bit into the receiver shift register.

The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are high. When communication is taking place, the bus is active. Only master devices can start a communication by causing a START condition on the bus. Normally, the data line is only allowed to change state when the clock line is low. If the data line changes state when the clock line is high, then the data line state is either a START condition or a STOP condition. A START condition is when the clock line is high and the data line goes from high to low. A STOP condition is when the clock line is high and the data line goes from low to high.

After the master issues a START condition, the master sends a byte that indicates which slave device to communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master sends an address in the address byte with a bit indicating whether to read from or write to the slave device.

Every byte transmitted on the I2C bus, address or data, is acknowledged with an acknowledge bit. When a master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master finishes reading a byte, the master pulls SDA low to acknowledge this operation to the slave. The master then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not present on the bus and the master attempts to address the device, the master receives a not-acknowledge because no device is present at that address to pull the line low.

When a master finishes communicating with a slave, the master can issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master can also issue another START condition. When a START condition is issued when the bus is active, this condition is called a repeated START condition.

The TLV320AIC3109-Q1 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave-address byte of 00h. Figure 29 and Figure 30 show timing diagrams for I2C write and read operations, respectively.

TLV320AIC3109-Q1 t0147-01_las510.gifFigure 29. I2C Write
TLV320AIC3109-Q1 t0148-01_las510.gifFigure 30. I2C Read

In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA are treated as data for the next incremental register.

Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an acknowledge, the slave takes over control of the SDA bus and transmits for the next 8 clocks the data of the next incremental register.