ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
The register map of the TLV320AIC3109-Q1 consists of two pages of registers, with each page containing 128 registers. The register at address zero on each page is used as a page-control register and writing to this register determines the active page for the device. All subsequent read/write operations access the page that is active at the time unless a register write is performed to change the active page. The active page defaults to page 0 on device reset.
Table 7 lists the different access codes used in the TLV320AIC3109-Q1 registers.
Access Type | Code | Description |
---|---|---|
R | R | Read |
R-W | R/W | Read or write |
W | W | Write |
-n | Value after reset or the default value |
The control registers for the TLV320AIC3109-Q1 are described in this section. All registers are 8 bits in width, with bit 7 referring to the most-significant bit of each register and bit 0 referring to the least-significant bit. Table 8 lists the registers for page 0 and page 1.
REGISTER | REGISTER DATA | |||||||
---|---|---|---|---|---|---|---|---|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
PAGE 0 REGISTERS | ||||||||
Register 0 | 0 | 0 | 0 | 0 | 0 | 0 | Page Select | |
Register 1 | Software Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Register 2 | ADC Sample Rate Select | DAC Sample Rate Select | ||||||
Register 3 | PLL Q | PLL Q | PLL P | |||||
Register 4 | PLL J | 0 | 0 | |||||
Register 5 | PLL D | |||||||
Register 6 | PLL D | 0 | 0 | |||||
Register 7 | fS(ref) Setting | DAC Dual-Rate Control | DAC Data Path Control | DAC Data Path Control | 0 | 0 | 0 | |
Register 8 | Word Clock Directional Control | Serial Output Data Driver | Bit, Word Clock Drive Control | Bit, Word Clock Drive Control | 0 | 0 | 0 | 0 |
Register 9 | Audio Serial Data Interface Transfer Mode | Bit Clock Rate Control | Bit Clock Rate Control | ADC Re-Sync | Re-Sync Mute Behavior | Re-Sync Mute Behavior | ||
Register 10 | Audio Serial Data Word Offset Control | |||||||
Register 11 | ADC Overflow Flag | 0 | DAC Overflow Flag | 0 | PLL R | |||
Register 12 | ADC High-Pass Filter Control | 0 | 0 | DAC De- Emphasis Filter Control | DAC De- Emphasis Filter Control | 0 | 0 | |
Register 13 | Headset Detection Control | Headset Type Detection Results | Headset Glitch Suppression Debounce Control for Button Press | Headset Glitch Suppression Debounce Control for Button Press | ||||
Register 14 | Driver Capacitive Coupling | 0 | 0 | Headset Detection Flag | 0 | 0 | 0 | 0 |
Register 15 | ADC PGA Mute | ADC PGA Gain Setting | ||||||
Register 16 | PGA_AUX Mute | PGA _AUX Gain Setting | ||||||
Register 19 | MIC1P/LINE1P Input Level Control for ADC PGA Mix | MIC1P/LINE1P Input Level Control for ADC PGA Mix | ADC PGA Soft-Stepping Control | ADC PGA Soft-Stepping Control | ||||
Register 21 | MIC2P/LINE2P Input Level Control for ADC PGA Mix | MIC2P/LINE2P Input Level Control for ADC PGA Mix | 0 | 0 | 0 | |||
Register 25 | MICBIAS Level Control | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 26 | AGC Enable | AGC Attack Time | AGC Decay Time | AGC Decay Time | ||||
Register 27 | AGC Maximum Gain Allowed | 0 | ||||||
Register 28 | Noise Gate Hysteresis Level Control | AGC Clip Stepping Control | AGC Clip Stepping Control | |||||
Register 32 | Channel Gain Applied by AGC Algorithm | |||||||
Register 34 | AGC Noise Detection Debounce Control | AGC Signal Detection Debounce Control | ||||||
Register 36 | ADC PGA Status | ADC Power Status | AGC Signal Detection Status | AGC Saturation Flag | 0 | 0 | 0 | 0 |
Register 37 | DAC Power Control | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Register 38 | 0 | 0 | HPCOM Output Driver Configuration Control | Short-Circuit Protection Control | Short-Circuit Protection Mode Control | 0 | ||
Register 40 | Output Common-Mode Voltage Control | 0 | 0 | 0 | 0 | Output Volume Control Soft- Stepping | ||
Register 41 | DAC Output Switching Control | 0 | 0 | 0 | 0 | 0 | 0 | |
Register 42 | Output Driver Power-On Delay Control | Driver Ramp-Up Step Timing Control | Weak Output Common-Mode Voltage Control | 0 | ||||
Register 43 | DAC Digital Mute | DAC Digital Volume Control Setting | ||||||
Register 60 | PGA Output Routing Control | PGA to HPOUT Analog Volume Control | ||||||
Register 61 | DAC_1 Output Routing Control | DAC_1 to HPOUT Analog Volume Control | ||||||
Register 63 | PGA_AUX Output Routing Control | PGA_AUX to HPOUT Analog Volume Control | ||||||
Register 65 | HPOUT Output Level Control | HPOUT Mute | HPOUT Power- Down Drive Control | HPOUT Volume Control Status | HPOUT Power Control | |||
Register 67 | PGA Output Routing Control | PGA to HPCOM Analog Volume Control | ||||||
Register 68 | DAC_1 Output Routing Control | DAC_1 to HPCOM Analog Volume Control | ||||||
Register 70 | PGA_AUX Output Routing Control | PGA_AUX to HPCOM Analog Volume Control | ||||||
Register 72 | HPCOM Output Level Control | HPCOM Mute | HPCOM Volume Control Status | HPCOM Volume Control Status | HPCOM Power Control | |||
Register 81 | PGA Output Routing Control | PGA to LEFT_LOP/M Analog Volume Control | ||||||
Register 82 | DAC_1 Output Routing Control | DAC_1 to LEFT_LOP/M Analog Volume Control | ||||||
Register 84 | PGA_AUX Output Routing Control | PGA_AUX to LEFT_LOP/M Analog Volume Control | ||||||
Register 86 | LEFT_LOP/M Output Level Control | LEFT_LOP/M Mute | 0 | LEFT_LOP/M Volume Control Status | LEFT_LOP/M Power Status | |||
Register 88 | PGA Output Routing Control | DAC_1 Output Routing Control | ||||||
Register 89 | DAC_1 Output Routing Control | DAC_1 to RIGHT_LOP/M Analog Volume Control | ||||||
Register 91 | PGA_AUX Output Routing Control | PGA_AUX to RIGHT_LOP/M Analog Volume Control | ||||||
Register 93 | RIGHT_LOP/M Output Level Control | RIGHT_LOP/M Mute | 0 | RIGHT_LOP/M Volume Control Status | RIGHT_LOP/M Power Status | |||
Register 94 | DAC Power Status | 0 | 0 | LEFT_LOP/M Power Status | RIGHT_LOP/M Power Status | 0 | HPOUT Driver Power Status | 0 |
Register 95 | 0 | HPOUT Short- Circuit Detection Status | 0 | HPCOM Short- Circuit Detection Status | 0 | HPCOM Power Status | 0 | 0 |
Register 96 | 0 | HPOUT Short- Circuit Detection Status | 0 | HPCOM Short- Circuit Detection Status | 0 | Headset Detection Status | ADC AGC Noise Gate Status | 0 |
Register 97 | 0 | HPOUT Short- Circuit Detection Status | 0 | HPCOM Short- Circuit Detection Status | 0 | Headset Detection Status | ADC AGC Noise Gate Status | 0 |
Register 101 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CODEC_CLKIN Source Selection |
Register 102 | CLKDIV_IN Source Selection | PLLCLK_IN Source Selection | 0 | 0 | 1 | 0 | ||
Register 103 | Attack Time Register Selection | Baseline AGC Attack Time | Multiplication Factor for Baseline AGC | 0 | 0 | |||
Register 104 | Decay Time Register Selection | Baseline AGC Decay Time | Multiplication Factor for Baseline AGC | 0 | 0 | |||
Register 107 | Channel High- Pass Filter Coefficient Selection | 0 | 0 | 0 | ADC Digital Output to Programmable Filter Path Selection | I2C Bus Condition Detector | 0 | I2C Bus Error Detection Status |
Register 108 | 0 | 0 | LINE1RM Path Selection | LINE1RP Path Selection | 0 | 0 | LINE1LM Path Selection | LINE1LP Path Selection |
Register 109 | DAC Current Adjustment | 0 | 0 | 0 | 0 | 0 | 0 | |
PAGE 1 REGISTERS | ||||||||
Register 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Page Select Bit |
Register 1 | Audio Effects Filter N0 Coefficient MSB | |||||||
Register 2 | Audio Effects Filter N0 Coefficient LSB | |||||||
Register 3 | Audio Effects Filter N1 Coefficient MSB | |||||||
Register 4 | Audio Effects Filter N1 Coefficient LSB | |||||||
Register 5 | Audio Effects Filter N2 Coefficient MSB | |||||||
Register 6 | Audio Effects Filter N2 Coefficient LSB | |||||||
Register 7 | Audio Effects Filter N3 Coefficient MSB | |||||||
Register 8 | Audio Effects Filter N3 Coefficient LSB | |||||||
Register 9 | Audio Effects Filter N4 Coefficient MSB | |||||||
Register 10 | Audio Effects Filter N4 Coefficient LSB | |||||||
Register 11 | Audio Effects Filter N5 Coefficient MSB | |||||||
Register 12 | Audio Effects Filter N5 Coefficient LSB | |||||||
Register 13 | Audio Effects Filter D1 Coefficient MSB | |||||||
Register 14 | Audio Effects Filter D1 Coefficient LSB | |||||||
Register 15 | Audio Effects Filter D2 Coefficient MSB | |||||||
Register 16 | Audio Effects Filter D2 Coefficient LSB | |||||||
Register 17 | Audio Effects Filter D4 Coefficient MSB | |||||||
Register 18 | Audio Effects Filter D4 Coefficient LSB | |||||||
Register 19 | Audio Effects Filter D5 Coefficient MSB | |||||||
Register 20 | Audio Effects Filter D5 Coefficient LSB | |||||||
Register 21 | De-Emphasis Filter N0 Coefficient MSB | |||||||
Register 22 | De-Emphasis Filter N0 Coefficient LSB | |||||||
Register 23 | De-Emphasis Filter N1 Coefficient MSB | |||||||
Register 24 | De-Emphasis Filter N1 Coefficient LSB | |||||||
Register 25 | De-Emphasis Filter D1 Coefficient MSB | |||||||
Register 26 | De-Emphasis Filter D1 Coefficient LSB | |||||||
Register 65 | ADC High-Pass Filter N0 Coefficient MSB | |||||||
Register 66 | Channel ADC High-Pass Filter N0 Coefficient LSB | |||||||
Register 67 | Channel ADC High-Pass Filter N1 Coefficient MSB | |||||||
Register 68 | Channel ADC High-Pass Filter N1 Coefficient LSB | |||||||
Register 69 | Channel ADC High-Pass Filter D1 Coefficient MSB | |||||||
Register 70 | Channel ADC High-Pass Filter D1 Coefficient LSB |