ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bit Clock Directional Control | Word Clock Directional Control | Serial Output Data Driver | Bit, Word Clock Drive Control | 0 | 0 | 0 | 0 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Bit Clock Directional Control | R/W | 0h | Bit clock directional control. 0: BCLK is an input (slave mode) 1: BCLK is an output (master mode) |
6 | Word Clock Directional Control | R/W | 0h | Word clock directional control. 0: WCLK is an input (slave mode) 1: WCLK is an output (master mode) |
5 | Serial Output Data Driver | R/W | 0h | Serial output data driver (DOUT) 3-state control. 0: Do not place DOUT in a high-impedance state when valid data are not being sent 1: Place DOUT in high-impedance state when valid data are not being sent |
4 | Bit, Word Clock Drive Control | R/W | 0h | Bit, word clock drive control. 0: BCLK, WCLK do not continue to be transmitted when running in master mode if the codec is powered down 1: BCLK, WCLK continue to be transmitted when running in master mode, even if the codec is powered down |
3 | Reserved | R | 0h | Reserved. Always write zeros to these bits. |
2:0 | Reserved | R/W | 0h | Reserved. Always write zeros to these bits. |