ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MIC1P/LINE1P Single-Ended vs Fully Differential Control | MIC1P/LINE1P Input Level Control for ADC PGA Mix | ADC Channel Power Control | ADC PGA Soft-Stepping Control | ||||
R/W-0h | R/W-1h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MIC1P/LINE1P Single-Ended vs Fully Differential Control | R/W | 0h | MIC1P/LINE1P single-ended vs fully differential control. 0: MIC1P/LINE1P is configured in single-ended mode 1: MIC1P/LINE1P and MIC1M/LINE1M are configured in fully differential mode |
6:3 | MIC1P/LINE1P Input Level Control for ADC PGA Mix | R/W | 1h | MIC1P/LINE1P input level control for ADC PGA mix. Setting the input level control to one of the following gains automatically connects LINE1L to the ADC PGA mix. 0000: Input level control gain = 0 dB 0001: Input level control gain = –1.5 dB 0010: Input level control gain = –3 dB 0011: Input level control gain = –4.5 dB 0100: Input level control gain = –6 dB 0101: Input level control gain = –7.5 dB 0110: Input level control gain = –9 dB 0111: Input level control gain = –10.5 dB 1000: Input level control gain = –12 dB 1001–1110: Reserved; do not write these sequences to these register bits 1111: LINE1L is not connected to the ADC PGA |
2 | ADC Channel Power Control | R/W | 0h | ADC channel power control. 0: ADC channel is powered down 1: ADC channel is powered up |
1:0 | ADC PGA Soft-Stepping Control | R/W | 0h | ADC PGA soft-stepping control. 00: ADC PGA soft-stepping at one time per sample period 01: ADC PGA soft-stepping at one time per two sample periods 10–11: ADC PGA soft-stepping is disabled |