ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC Overflow Flag | 0 | DAC Overflow Flag | 0 | PLL R | |||
R-0h | R-0h | R-0h | R-0h | R/W-0001h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ADC Overflow Flag | R | 0h | ADC overflow flag. This bit is a sticky bit, which stays set if an overflow occurs, even if the overflow condition is removed. The register bit is reset to 0 after being read. 0: No overflow has occurred 1: An overflow has occurred |
6 | Reserved | R | 0h | Reserved. Always write zero to this bit. |
5 | DAC Overflow Flag | R | 0h | DAC overflow flag. This bit is a sticky bit, which stays set if an overflow occurs, even if the overflow condition is removed. The register bit is reset to 0 after being read. 0: No overflow has occurred 1: An overflow has occurred |
4 | Reserved | R | 0h | Reserved. Always write zero to this bit. |
3:0 | PLL R | R/W | 0001h | PLL R value. 0000: R = 16 0001: R = 1 0010: R = 2 0011: R = 3 0100: R = 4 … 1110: R = 14 1111: R = 15 |