ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Audio Serial Data Interface Transfer Mode | Audio Serial Data Word Length Control | Bit Clock Rate Control | DAC Re-Sync | ADC Re-Sync | Re-Sync Mute Behavior | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:6 | Audio Serial Data Interface Transfer Mode | R/W | 0h | Audio serial data interface transfer mode. 00: Serial data bus uses I2S mode 01: Serial data bus uses DSP mode 10: Serial data bus uses right-justified mode 11: Serial data bus uses left-justified mode |
5:4 | Audio Serial Data Word Length Control | R/W | 0h | Audio serial data word length control. 00: Audio data word length = 16 bits 01: Audio data word length = 20 bits 10: Audio data word length = 24 bits 11: Audio data word length = 32 bits |
3 | Bit Clock Rate Control | R/W | 0h | Bit clock rate control. This register only has effect when the bit clock is programmed as an output. 0: Continuous-transfer mode used to determine master mode bit clock rate 1: 256-clock transfer mode used, resulting in 256 bit clocks per frame |
2 | DAC Re-Sync | R/W | 0h | DAC re-sync. 0: Don’t care 1: Re-sync mono DAC with codec interface if the group delay changes by more than ±DAC (fS / 4) |
1 | ADC Re-Sync | R/W | 0h | ADC re-sync. 0: Don’t care 1: Re-sync mono ADC with codec interface if the group delay changes by more than ±ADC (fS / 4) |
0 | Re-Sync Mute Behavior | R/W | 0h | Re-sync mute behavior. 0: Re-sync is done without soft-muting the channel (ADC or DAC) 1: Re-sync is done by internally soft-muting the channel (ADC or DAC) |