ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Audio Serial Data Word Offset Control | |||||||
R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:0 | Audio Serial Data Word Offset Control | R/W | 0h | Audio serial data word offset control. This register determines where valid data are placed or expected in each frame by controlling the offset from beginning of the frame where valid data begins. The offset is measured from the rising edge of the word clock when in DSP mode. 0000 0000: Data offset = 0 bit clocks 0000 0001: Data offset = 1 bit clock 0000 0010: Data offset = 2 bit clocks … Note: In continuous transfer mode the maximum offset is 17 for the I2S, left-justified format, and right-justified format modes and 16 for DSP mode. In 256-clock mode, the maximum offset is 242 for the I2S, left-justified format, and right-justified format modes and 241 for DSP modes. 1111 1110: Data offset = 254 bit clocks 1111 1111: Data offset = 255 bit clocks |