ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
Occasionally, some systems can encounter noise or glitches on the I2C bus. In the unlikely event that this noise affects bus performance, use the I2C debug register. This feature terminates the I2C bus error allowing the I2C device and system to resume communications. The I2C bus error detector is enabled by default. The TLV320AIC3109-Q1 I2C error detector status can be read from bit 0 in register 107, page 0. If desired, the detector can be disabled by writing to bit 2 in register 107, page 0.