ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL D | 0 | 0 | |||||
R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:2 | PLL D(1) | R/W | 0h | These bits control the PLL D value. The six least-significant bits of a 14-bit unsigned integer valid values for D are from 0 to 9999, represented by a 14-bit integer located in registers 5–6, page 0. Do not write values into these registers that result in a D value outside the valid range. |
1:0 | Reserved | R/W | 0h | Reserved. Always write zeros to these bits. |