ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
The TLV320AIC3109-Q1 includes a mono audio ADC that uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 96 kHz. Whenever the ADC or DAC is in operation, the device requires that an audio master clock be provided and appropriate audio clock generation be set up within the device.
The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 fS to the final output sampling rate of fS. The decimation filter provides a linear phase output response with a group delay of 17 / fS. The –3-dB bandwidth of the decimation filter extends to 0.45 fS and scales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stop band from 0.55 fS to 64 fS. The device also provide options to select the corner frequency of the digital high-pass filter.
Requirements for analog antialiasing filtering are very relaxed because of the oversampling nature of the audio ADC and the integrated digital decimation filtering. The TLV320AIC3109-Q1 integrates a second-order analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient antialiasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA) that allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see registers 19 and 22, page 0). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power-down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft-stepping is enabled, the audio master clock must be applied to the device after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC power-down flag is no longer set, the audio master clock can be shut down.
An additional auxiliary PGA is provided to allow the mixing of the DAC output signals with an input not routed through the ADC. This PGA has the same specifications as the ADC PGA.