ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Channel High-Pass Filter Coefficient Selection | 0 | 0 | 0 | ADC Digital Output to Programmable Filter Path Selection | I2C Bus Condition Detector | 0 | I2C Bus Error Detection Status |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Channel High-Pass Filter Coefficient Selection | R/W | 0h | Channel high-pass filter coefficient selection. 0: Default coefficients are used when ADC high pass is enabled 1: Programmable coefficients are used when ADC high pass is enabled |
6:4 | Reserved | R/W | 0h | Reserved. Always write zeros to these bits. |
3 | ADC Digital Output to Programmable Filter Path Selection | R/W | 0h | ADC digital output to programmable filter path selection. 0: No additional programmable filters other than the HPF are used for the ADC 1: The programmable filter is connected to the ADC output if both DACs are powered down |
2 | I2C Bus Condition Detector | R/W | 0h | I2C bus condition detector. 0: Internal logic is enabled to detect an I2C bus error and clears the bus error condition 1: Internal logic is disabled to detect an I2C bus error |
1 | Reserved | R | 0h | Reserved. Always write zero to this bit |
0 | I2C Bus Error Detection Status | R | 0h | I2C bus error detection status. 0: I2C bus error is not detected 1: I2C bus error is detected; this bit is cleared by reading this register |