The UART can generate interrupts when the following conditions are observed:
- Overrun error
- Break error
- Parity error
- Framing error
- Receive time-out
- Transmit (when the condition defined in the UART:IFLS TXSEL register bit is
met)
- Receive (when the condition defined in the UART:IFLS RXSEL register bit is
met)
- End of transmission (when no data on TX line and TX FIFO underflow
- RX DMA Done
- TX DMA Done
All of the interrupt events are ORed
together before being sent to the MCU event fabric, so the UART can only generate a
single interrupt request at any given time. Software can service multiple interrupt
events in a single interrupt service routine (ISR) by reading the UART Masked
Interrupt Status Register (UART.MIS).
The interrupt events that can trigger
a controller-level interrupt are defined in the UART Interrupt Mask Register
(UART.IMSC) by setting the corresponding bits. If interrupts are not used, the raw
interrupt status is always visible through the UART Raw Interrupt Status Register
(UART.RIS).
Interrupts can be cleared (for the
UART.MIS and UART.RIS registers) by setting the corresponding bit in the UART
Interrupt Clear Register (UART.ICR).
The receive time-out interrupt is
asserted when the RX FIFO is not empty, and no further data is received over a
32-bit period. The receive time-out interrupt is cleared either when the FIFO
becomes empty through reading all the data (or by reading the holding register), or
when the corresponding bit in the UART.ICR register is set.
The UART module provides the
possibility of setting and clearing masks for every individual interrupt source
using the UART Interrupt Mask Set/Clear Register (UART.IMSC). The five events that
can cause combined interrupts to CPU are:
- RX: The receive interrupt changes state when one of the following events
occurs:
- If the FIFOs are enabled and the receive FIFO reaches the programmed
trigger level. When this happens, the receive interrupt is asserted
high. The receive interrupt is cleared by reading data from the receive
FIFO until it becomes less than the trigger level, or by clearing the
interrupt.
- If the FIFOs are disabled (have a depth of one location) and data is
received, thereby filling the location, the receive interrupt is
asserted high. The receive interrupt is cleared by performing a single
read of the receive FIFO, or by clearing the interrupt.
- TX: The transmit interrupt changes state when one of the following events
occurs:
- If the FIFOs are enabled and the transmit FIFO is equal to or lower than
the programmed trigger level, then the transmit interrupt is asserted
high. The transmit interrupt is cleared by writing data to the transmit
FIFO until it becomes greater than the trigger level, or by clearing the
interrupt.
- If the FIFOs are disabled (have a depth of one location) and there is
no data present in the transmitters single location, the transmit
interrupt is asserted high. The interrupt is cleared by performing a
single write to the transmit FIFO, or by clearing the interrupt.
- RX time-out: The receive time-out interrupt is asserted when the receive FIFO is
not empty, and no more data is received during a 32-bit period. The receive
time-out interrupt is cleared either when the FIFO becomes empty through reading
all the data (or by reading the holding register), or when 1 is written to the
corresponding bit of the Interrupt Clear Register (UART:ICR).
- Modem status: The modem status
interrupt is asserted if the modem status signal CTS toggles. It can be cleared
using the corresponding clear bit in the UART.ICR register.
- Error: The error interrupt is asserted when an error occurs in the reception of
data by the UART. The interrupt can be caused by a number of different error
conditions:
- framing
- parity
- break
- overrun
The cause of the interrupt can be
determined by reading the UART.RIS register or the UART.MIS register. The interrupt
can be cleared by writing to the relevant bits of the UART.ICR register.
In addition to the five events produced by the UART module, two additional events are
ORed to the interrupt line:
- RX DMA done: Indicates that the
receiver µDMA task has completed. This is a level interrupt provided by the µDMA
module
- TX DMA done: Indicates that the
transmit µDMA task has completed. This is a level interrupt provided by the µDMA
module