Each timer can generate an Interrupt request, ADC trigger and DMA request output
event. These output events can be triggered on different internal timer events. The
different internal events can be viewed in the RIS register.
If one or more of the fields in the IMASK register are set high, the timer sends out
an interrupt event when the internal timer event corresponding to the fields set in
IMASK occur.
These internal timer events can also set the ADC trigger or DMA request depending on
the configuration of the ADCTRG.SRC and DMA.REQ field. That is, the ADC trigger and
DMA request output events are generated when the corresponding interrupt is set in
the RIS register.
Below are some important side effects regarding the Interrupts, ADC trigger and DMA
request.
- Reading/writing to the CnCC or PCnCC register shall clear the corresponding
channel interrupt.
- Reading/writing to NC (No Clear) registers does not have any side effects on
interrupts.
- Reading/writing to PTGT or TGT clears both RIS.ZERO and RIS.TGT.
- The CMP interrupts are updated on the timer clock. These interrupts trigger at
the same time as an CMP event.
- The ZERO and TGT interrupts
trigger after one system clock cycle when CNTR = ZERO/TARGET.
- The field CTL.INTP gets set when the ZERO and TGT interrupts are set. This field
decides if the interrupts are set on the beginning of the timer period or on the
end of the timer period.
- The RIS.ZERO interrupt is not set when starting the timer.
- Note that if you have a short
timer period, and you have configured the LGPT to set the interrupt output on
both ZERO and TGT, you can accidentally clear both ZERO and TGT when
reading/writing to PTGT/TGT. This depends on the CPU's response time. If you
want to make sure both the ZERO and TGT interrupts are received, use
PTGTNC/TGTNC and clear the corresponding interrupt by writing to RIS.ICLR.
- If the µDMA request is used in
addition to the interrupt make sure that a write/read does not clear unhandled
interrupt requests. As an example, if the µDMA updates PTGT on ZERO interrupt
and the CPU does some external handling on TGT interrupt, then if the timer
period is short, the µDMA write to PTGT can clear the unhandled TGT interrupt.
This can be avoided by letting the µDMA write to PTGTNC and letting the CPU
clear both TGT and ZERO