SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

22.5 LRFDDBELL Registers

Table 22-1 lists the memory-mapped registers for the LRFDDBELL registers. All register offset addresses not listed in Table 22-1 should be considered as reserved locations and the register contents should not be modified.

Table 22-1 LRFDDBELL Registers
OffsetAcronymRegister NameSection
0hDESCDescriptionGo
4hCLKCTLClock controlGo
8hDMACFGDMA ConfigurationGo
ChSYSTIMOEVSystimer Output Event Control RegisterGo
10hSYSTDMATRIGSystem DMA TriggerGo
14hGPOSEL0GPO controlGo
18hGPOSEL1GPO controlGo
44hIMASK0Interrupt maskGo
48hRIS0Raw interrupt statusGo
4ChMIS0Masked interrupt statusGo
50hISET0Interrupt setGo
54hICLR0Interrupt clearGo
84hIMASK1Interrupt maskGo
88hRIS1Raw interrupt statusGo
8ChMIS1Masked interrupt statusGo
90hISET1Interrupt setGo
94hICLR1Interrupt clearGo
C4hIMASK2Interrupt maskGo
C8hRIS2Raw interrupt statusGo
CChMIS2Masked interrupt statusGo
D0hISET2Interrupt setGo
D4hICLR2Interrupt clearGo

Complex bit access types are encoded to fit into small table cells. Table 22-2 shows the codes that are used for access types in this section.

Table 22-2 LRFDDBELL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

22.5.1 DESC Register (Offset = 0h) [Reset = 01411010h]

DESC is shown in Table 22-3.

Return to the Summary Table.

Description.
This register identifies the peripheral and its exact version.

Table 22-3 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR/W141hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR/W1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0h = STDIP MMRs do not exist
1h = These MMRs begin at offset 64*STDIPOFF from IP base address
11-8INSTNUMR/W0hIP Instance Number. If multiple instances of IP exist in the device, this field can identify the instance number
7-4MAJREVR/W1hMajor rev of the IP
3-0MINREVR/W0hMinor rev of the IP

22.5.2 CLKCTL Register (Offset = 4h) [Reset = 00000001h]

CLKCTL is shown in Table 22-4.

Return to the Summary Table.

Controls the functional clock gates for the individual sub-modules.
Writing a bit to zero does not necessarily switch off the corresponding clock. It can also be requested internally.
A clock will only be switched off if internal and external requests are removed

Table 22-4 CLKCTL Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13DEMR/W0hEnable the clock to the demodulator. The modem will request this clock automatically. This bit is to force the clock to be free running
0h = Clock not requested
1h = Clock is requested
12MODR/W0hEnable the clock to the modulator. Modem will request this clock automatically, this bit is to force the modulator clock to be free running.
0h = Clock not requested
1h = Clock is requested
11S2RRAMR/W0hEnable the clock to the S2R RAM
0h = Clock not requested
1h = Clock is requested
10BUFRAMR/W0hEnable the clock to the BUFRAM
0h = Clock not requested
1h = Clock is requested
9DSBRAMR/W0hEnable the clock to the DSB RAM
0h = Clock not requested
1h = Clock is requested
8RFERAMR/W0hEnable the clock to the RFE RAM
0h = Clock not requested
1h = Clock is requested
7MCERAMR/W0hEnable the clock to the MCE RAM
0h = Clock not requested
1h = Clock is requested
6PBERAMR/W0hEnable the clock to the PBE RAM
0h = Clock not requested
1h = Clock is requested
5TRCR/W0hEnable the clock to the Tracer
0h = Clock not requested
1h = Clock is requested
4S2RR/W0hEnable the clock to Samples2RAM
0h = Clock not requested
1h = Clock is requested
3RFER/W0hEnable the clock to the RFE
0h = Clock not requested
1h = Clock is requested
2MDMR/W0hEnable the clock to the Modem
0h = Clock not requested
1h = Clock is requested
1PBER/W0hEnable the clock to the PBE
0h = Clock not requested
1h = Clock is requested
0BRIDGER/W1hClock enable to AHB bridge. The bridge will request it's own clock, this bit it to override that feature to have a free running clock.
0h = Clock not requested
1h = Clock is requested

22.5.3 DMACFG Register (Offset = 8h) [Reset = 00000000h]

DMACFG is shown in Table 22-5.

Return to the Summary Table.

DMA Configuration

Table 22-5 DMACFG Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-1TRIGSRCR/W0hSelect DMA trigger source
0h = The DMA is triggered by the PBE FW trigger
1h = The DMA is triggered by the MCE FW trigger
2h = The DMA is triggered by the MCE FW trigger
3h = The DMA is triggered from the FIFO. See the FIFO configration register for what FIFO event will generate the trigger
0ENR/W0hEnables the DMA interface
0h = Disable DMA interface, no activity on interface
1h = Enable DMA interface. The triggers are able to give activity on the interface

22.5.4 SYSTIMOEV Register (Offset = Ch) [Reset = 00000000h]

SYSTIMOEV is shown in Table 22-6.

Return to the Summary Table.

Systimer Output Event Control Register.
Controls routing of internal events to the three systimer output events

Table 22-6 SYSTIMOEV Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-8SRC2R/W0hSelect source of systimer output event 2 (capture source)
0h = Output not enabled, always 0.
1h = RFE FW systimer capture event 0
2h = RFE FW systimer capture event 1
3h = RFE FW systimer capture event 2
4h = MCE FW systimer capture event 0
5h = MCE FW systimer capture event 1
6h = MCE FW systimer capture event 2
7h = MDM HW event 0
8h = MDM HW event 1
9h = MDM HW event 2
Ah = PBE FW systimer capture event 0
Bh = PBE FW systimer capture event 1
Ch = PBE FW systimer capture event 2
7-4SRC1R/W0hSelect source of systimer output event 1 (capture source)
0h = Output not enabled, always 0.
1h = RFE FW systimer capture event 0
2h = RFE FW systimer capture event 1
3h = RFE FW systimer capture event 2
4h = MCE FW systimer capture event 0
5h = MCE FW systimer capture event 1
6h = MCE FW systimer capture event 2
7h = MDM HW event 0
8h = MDM HW event 1
9h = MDM HW event 2
Ah = PBE FW systimer capture event 0
Bh = PBE FW systimer capture event 1
Ch = PBE FW systimer capture event 2
3-0SRC0R/W0hSelect source of systimer output event 0 (capture source)
0h = Output not enabled, always 0.
1h = RFE FW systimer capture event 0
2h = RFE FW systimer capture event 1
3h = RFE FW systimer capture event 2
4h = MCE FW systimer capture event 0
5h = MCE FW systimer capture event 1
6h = MCE FW systimer capture event 2
7h = MDM HW event 0
8h = MDM HW event 1
9h = MDM HW event 2
Ah = PBE FW systimer capture event 0
Bh = PBE FW systimer capture event 1
Ch = PBE FW systimer capture event 2

22.5.5 SYSTDMATRIG Register (Offset = 10h) [Reset = 00000000h]

SYSTDMATRIG is shown in Table 22-7.

Return to the Summary Table.

System DMA Trigger
Manual triggering of systimer capture event or DMA trigger
This comes on top of any HW driven sources configured in SYSTIMOEV

Table 22-7 SYSTDMATRIG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3DMAW0hTrigger a DMA request from the Radio
0h = DMA not manually triggered
1h = DMA request manually triggered
2SYST2W0hTrigger a capture event on systimer event 0 from the radio
0h = Not capture event triggered
1h = Capture event triggered
1SYST1W0hTrigger a capture event on systimer event 0 from the radio
0h = Not capture event triggered
1h = Capture event triggered
0SYST0W0hTrigger a capture event on systimer event 0 from the radio
0h = Not capture event triggered
1h = Capture event triggered

22.5.6 GPOSEL0 Register (Offset = 14h) [Reset = 00000000h]

GPOSEL0 is shown in Table 22-8.

Return to the Summary Table.

Controls routing of GPO signals from MDM, RFE and PBE to the radio GPO lines

Table 22-8 GPOSEL0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24SRC3R/W0hSelect source of radio GPO line 3
0h = Output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 3
23-21RESERVEDR0hReserved
20-16SRC2R/W0hSelect source of radio GPO line 2
0h = Output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 2
15-13RESERVEDR0hReserved
12-8SRC1R/W0hSelect source of radio GPO line 1
0h = Output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 1
7-5RESERVEDR0hReserved
4-0SRC0R/W0hSelect source of radio GPO line 0
0h = Output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 0

22.5.7 GPOSEL1 Register (Offset = 18h) [Reset = 00000000h]

GPOSEL1 is shown in Table 22-9.

Return to the Summary Table.

Controls routing of GPO signals from MDM, RFE and PBE to the radio GPO lines

Table 22-9 GPOSEL1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24SRC7R/W0hSelect source of radio GPO line 7
0h = No output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 7
23-21RESERVEDR0hReserved
20-16SRC6R/W0hSelect source of radio GPO line 6
0h = No output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Selevt RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 6
15-13RESERVEDR0hReserved
12-8SRC5R/W0hSelect source of radio GPO line 5
0h = No output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 5
7-5RESERVEDR0hReserved
4-0SRC4R/W0hSelect source of radio GPO line 4
0h = No output not enabled
1h = Select PBE GPO line 0
2h = Select PBE GPO line 1
3h = Select PBE GPO line 2
4h = Select PBE GPO line 3
5h = Select PBE GPO line 4
6h = Select PBE GPO line 5
7h = Select PBE GPO line 6
8h = Select PBE GPO line 7
9h = Select MCE GPO line 0
Ah = Select MCE GPO line 1
Bh = Select MCE GPO line 2
Ch = Select MCE GPO line 3
Dh = Select MCE GPO line 4
Eh = Select MCE GPO line 5
Fh = Select MCE GPO line 6
10h = Select MCE GPO line 7
11h = Select RFE GPO line 0
12h = Select RFE GPO line 1
13h = Select RFE GPO line 2
14h = Select RFE GPO line 3
15h = Select RFE GPO line 4
16h = Select RFE GPO line 5
17h = Select RFE GPO line 6
18h = Select RFE GPO line 7
19h = Select RFCTRC GPO line 4

22.5.8 IMASK0 Register (Offset = 44h) [Reset = 00000000h]

IMASK0 is shown in Table 22-10.

Return to the Summary Table.

Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 22-10 IMASK0 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
30SYSTIM1R/W0hSYSTIM1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
29SYSTIM0R/W0hSYSTIM0 event
0h = Disable interrupt mask
1h = Enable interrupt mask
28MDMDONER/W0hMDMDONE event
0h = Disable interrupt mask
1h = Enable interrupt mask
27MDMINR/W0hMDMIN event
0h = Disable interrupt mask
1h = Enable interrupt mask
26MDMOUTR/W0hMDMOUT event
0h = Disable interrupt mask
1h = Enable interrupt mask
25MDMSOFT2R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
24MDMSOFT1R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
23MDMSOFT0R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
22RFEDONER/W0hRFEDONE event
0h = Disable interrupt mask
1h = Enable interrupt mask
21RFESOFT1R/W0hRFESOFT1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
20RFESOFT0R/W0hRFESOFT0 event
0h = Disable interrupt mask
1h = Enable interrupt mask
19LOCKR/W0hLOCK event
0h = Disable interrupt mask
1h = Enable interrupt mask
18LOLR/W0hLOSS_OF_LOCK event
0h = Disable interrupt mask
1h = Enable interrupt mask
17TXFIFOR/W0hTXFIFO event
0h = Disable interrupt mask
1h = Enable interrupt mask
16RXFIFOR/W0hRXFIFO event
0h = Disable interrupt mask
1h = Enable interrupt mask
15PBE15R/W0hPBE15 event
0h = Disable interrupt mask
1h = Enable interrupt mask
14PBE14R/W0hPBE14 event
0h = Disable interrupt mask
1h = Enable interrupt mask
13PBE13R/W0hPBE13 event
0h = Disable interrupt mask
1h = Enable interrupt mask
12PBE12R/W0hPBE12 event
0h = Disable interrupt mask
1h = Enable interrupt mask
11PBE11R/W0hPBE11 event
0h = Disable interrupt mask
1h = Enable interrupt mask
10PBE10R/W0hPBE10 event
0h = Disable interrupt mask
1h = Enable interrupt mask
9RESERVEDR0hReserved
8PBE8R/W0hPBE8 event
0h = Disable interrupt mask
1h = Enable interrupt mask
7PBE7R/W0hPBE7 event
0h = Disable interrupt mask
1h = Enable interrupt mask
6PBE6R/W0hPBE6 event
0h = Disable interrupt mask
1h = Enable interrupt mask
5PBE5R/W0hPBE5 event
0h = Disable interrupt mask
1h = Enable interrupt mask
4PBE4R/W0hPBE4 event
0h = Disable interrupt mask
1h = Enable interrupt mask
3PBE3R/W0hPBE3 event
0h = Disable interrupt mask
1h = Enable interrupt mask
2PBE2R/W0hPBE2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
1PBE1R/W0hPBE1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
0PBE0R/W0hPBE0 event
0h = Disable interrupt mask
1h = Enable interrupt mask

22.5.9 RIS0 Register (Offset = 48h) [Reset = 00000000h]

RIS0 is shown in Table 22-11.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 22-11 RIS0 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R0hSYSTIM2 event
0h = Interrupt did not occur
1h = Interrupt occurred
30SYSTIM1R0hSYSTIM1 event
0h = Interrupt did not occur
1h = Interrupt occurred
29SYSTIM0R0hSYSTIM0 event
0h = Interrupt did not occur
1h = Interrupt occurred
28MDMDONER0hMDMDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
27MDMINR0hMDMIN event
0h = Interrupt did not occur
1h = Interrupt occurred
26MDMOUTR0hMDMOUT event
0h = Interrupt did not occur
1h = Interrupt occurred
25MDMSOFT2R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
24MDMSOFT1R0hMDMSOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
23MDMSOFT0R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
22RFEDONER0hRFEDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
21RFESOFT1R0hRFESOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
20RFESOFT0R0hRFESOFT0 event
0h = Interrupt did not occur
1h = Interrupt occurred
19LOCKR0hLOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
18LOLR0hLOSS_OF_LOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
17TXFIFOR0hTXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
16RXFIFOR0hRXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
15PBE15R0hPBE15 event
0h = Interrupt did not occur
1h = Interrupt occurred
14PBE14R0hPBE14 event
0h = Interrupt did not occur
1h = Interrupt occurred
13PBE13R0hPBE13 event
0h = Interrupt did not occur
1h = Interrupt occurred
12PBE12R0hPBE12 event
0h = Interrupt did not occur
1h = Interrupt occurred
11PBE11R0hPBE11 event
0h = Interrupt did not occur
1h = Interrupt occurred
10PBE10R0hPBE10 event
0h = Interrupt did not occur
1h = Interrupt occurred
9PBE9R0hPBE9 event
0h = Interrupt did not occur
1h = Interrupt occurred
8PBE8R0hPBE8 event
0h = Interrupt did not occur
1h = Interrupt occurred
7PBE7R0hPBE7 event
0h = Interrupt did not occur
1h = Interrupt occurred
6PBE6R0hPBE6 event
0h = Interrupt did not occur
1h = Interrupt occurred
5PBE5R0hPBE5 event
0h = Interrupt did not occur
1h = Interrupt occurred
4PBE4R0hPBE4 event
0h = Interrupt did not occur
1h = Interrupt occurred
3PBE3R0hPBE3 event
0h = Interrupt did not occur
1h = Interrupt occurred
2PBE2R0hPBE2 event
0h = Interrupt did not occur
1h = Interrupt occurred
1PBE1R0hPBE1 event
0h = Interrupt did not occur
1h = Interrupt occurred
0PBE0R0hPBE0 event
0h = Interrupt did not occur
1h = Interrupt occurred

22.5.10 MIS0 Register (Offset = 4Ch) [Reset = 00000000h]

MIS0 is shown in Table 22-12.

Return to the Summary Table.

Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 22-12 MIS0 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R0hSYSTIM2 event
0h = Interrupt did not occur
1h = Interrupt occurred
30SYSTIM1R0hSYSTIM1 event
0h = Interrupt did not occur
1h = Interrupt occurred
29SYSTIM0R0hSYSTIM0 event
0h = Interrupt did not occur
1h = Interrupt occurred
28MDMDONER0hMDMDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
27MDMINR0hMDMIN event
0h = Interrupt did not occur
1h = Interrupt occurred
26MDMOUTR0hMDMOUT event
0h = Interrupt did not occur
1h = Interrupt occurred
25MDMSOFT2R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
24MDMSOFT1R0hMDMSOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
23MDMSOFT0R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
22RFEDONER0hRFEDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
21RFESOFT1R0hRFESOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
20RFESOFT0R0hRFESOFT0 event
0h = Interrupt did not occur
1h = Interrupt occurred
19LOCKR0hLOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
18LOLR0hLOSS_OF_LOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
17TXFIFOR0hTXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
16RXFIFOR0hRXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
15PBE15R0hPBE15 event
0h = Interrupt did not occur
1h = Interrupt occurred
14PBE14R0hPBE14 event
0h = Interrupt did not occur
1h = Interrupt occurred
13PBE13R0hPBE13 event
0h = Interrupt did not occur
1h = Interrupt occurred
12PBE12R0hPBE12 event
0h = Interrupt did not occur
1h = Interrupt occurred
11PBE11R0hPBE11 event
0h = Interrupt did not occur
1h = Interrupt occurred
10PBE10R0hPBE10 event
0h = Interrupt did not occur
1h = Interrupt occurred
9PBE9R0hPBE9 event
0h = Interrupt did not occur
1h = Interrupt occurred
8PBE8R0hPBE8 event
0h = Interrupt did not occur
1h = Interrupt occurred
7PBE7R0hPBE7 event
0h = Interrupt did not occur
1h = Interrupt occurred
6PBE6R0hPBE6 event
0h = Interrupt did not occur
1h = Interrupt occurred
5PBE5R0hPBE5 event
0h = Interrupt did not occur
1h = Interrupt occurred
4PBE4R0hPBE4 event
0h = Interrupt did not occur
1h = Interrupt occurred
3PBE3R0hPBE3 event
0h = Interrupt did not occur
1h = Interrupt occurred
2PBE2R0hPBE2 event
0h = Interrupt did not occur
1h = Interrupt occurred
1PBE1R0hPBE1 event
0h = Interrupt did not occur
1h = Interrupt occurred
0PBE0R0hPBE0 event
0h = Interrupt did not occur
1h = Interrupt occurred

22.5.11 ISET0 Register (Offset = 50h) [Reset = 00000000h]

ISET0 is shown in Table 22-13.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 22-13 ISET0 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Writing 0 has no effect
1h = Set Interrupt
30SYSTIM1R/W0hSYSTIM1 event
0h = Writing 0 has no effect
1h = Set Interrupt
29SYSTIM0R/W0hSYSTIM0 event
0h = Writing 0 has no effect
1h = Set Interrupt
28MDMDONER/W0hMDMDONE event
0h = Writing 0 has no effect
1h = Set Interrupt
27MDMINR/W0hMDMIN event
0h = Writing 0 has no effect
1h = Set Interrupt
26MDMOUTR/W0hMDMOUT event
0h = Writing 0 has no effect
1h = Set Interrupt
25MDMSOFT2R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Set Interrupt
24MDMSOFT1R/W0hMDMSOFT1 event
0h = Writing 0 has no effect
1h = Set Interrupt
23MDMSOFT0R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Set Interrupt
22RFEDONER/W0hRFEDONE event
0h = Writing 0 has no effect
1h = Set Interrupt
21RFESOFT1R/W0hRFESOFT1 event
0h = Writing 0 has no effect
1h = Set Interrupt
20RFESOFT0R/W0hRFESOFT0 event
0h = Writing 0 has no effect
1h = Set Interrupt
19LOCKR/W0hLOCK event
0h = Writing 0 has no effect
1h = Set Interrupt
18LOLR/W0hLOSS_OF_LOCK event
0h = Writing 0 has no effect
1h = Set Interrupt
17TXFIFOR/W0hTXFIFO event
0h = Writing 0 has no effect
1h = Set Interrupt
16RXFIFOR/W0hRXFIFO event
0h = Writing 0 has no effect
1h = Set Interrupt
15PBE15R/W0hPBE15 event
0h = Writing 0 has no effect
1h = Set Interrupt
14PBE14R/W0hPBE14 event
0h = Writing 0 has no effect
1h = Set Interrupt
13PBE13R/W0hPBE13 event
0h = Writing 0 has no effect
1h = Set Interrupt
12PBE12R/W0hPBE12 event
0h = Writing 0 has no effect
1h = Set Interrupt
11PBE11R/W0hPBE11 event
0h = Writing 0 has no effect
1h = Set Interrupt
10PBE10R/W0hPBE10 event
0h = Writing 0 has no effect
1h = Set Interrupt
9PBE9R/W0hPBE9 event
0h = Writing 0 has no effect
1h = Set Interrupt
8PBE8R/W0hPBE8 event
0h = Writing 0 has no effect
1h = Set Interrupt
7PBE7R/W0hPBE7 event
0h = Writing 0 has no effect
1h = Set Interrupt
6PBE6R/W0hPBE6 event
0h = Writing 0 has no effect
1h = Set Interrupt
5PBE5R/W0hPBE5 event
0h = Writing 0 has no effect
1h = Set Interrupt
4PBE4R/W0hPBE4 event
0h = Writing 0 has no effect
1h = Set Interrupt
3PBE3R/W0hPBE3 event
0h = Writing 0 has no effect
1h = Set Interrupt
2PBE2R/W0hPBE2 event
0h = Writing 0 has no effect
1h = Set Interrupt
1PBE1R/W0hPBE1 event
0h = Writing 0 has no effect
1h = Set Interrupt
0PBE0R/W0hPBE0 event
0h = Writing 0 has no effect
1h = Set Interrupt

22.5.12 ICLR0 Register (Offset = 54h) [Reset = 00000000h]

ICLR0 is shown in Table 22-14.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 22-14 ICLR0 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
30SYSTIM1R/W0hSYSTIM1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
29SYSTIM0R/W0hSYSTIM0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
28MDMDONER/W0hMDMDONE event
0h = Writing 0 has no effect
1h = Clear Interrupt
27MDMINR/W0hMDMIN event
0h = Writing 0 has no effect
1h = Clear Interrupt
26MDMOUTR/W0hMDMOUT event
0h = Writing 0 has no effect
1h = Clear Interrupt
25MDMSOFT2R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Clear Interrupt
24MDMSOFT1R/W0hMDMSOFT1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
23MDMSOFT0R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Clear Interrupt
22RFEDONER/W0hRFEDONE event
0h = Writing 0 has no effect
1h = Clear Interrupt
21RFESOFT1R/W0hRFESOFT1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
20RFESOFT0R/W0hRFESOFT0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
19LOCKR/W0hLOCK event
0h = Writing 0 has no effect
1h = Clear Interrupt
18LOLR/W0hLOSS_OF_LOCK event
0h = Writing 0 has no effect
1h = Clear Interrupt
17TXFIFOR/W0hTXFIFO event
0h = Writing 0 has no effect
1h = Clear Interrupt
16RXFIFOR/W0hRXFIFO event
0h = Writing 0 has no effect
1h = Clear Interrupt
15PBE15R/W0hPBE15 event
0h = Writing 0 has no effect
1h = Clear Interrupt
14PBE14R/W0hPBE14 event
0h = Writing 0 has no effect
1h = Clear Interrupt
13PBE13R/W0hPBE13 event
0h = Writing 0 has no effect
1h = Clear Interrupt
12PBE12R/W0hPBE12 event
0h = Writing 0 has no effect
1h = Clear Interrupt
11PBE11R/W0hPBE11 event
0h = Writing 0 has no effect
1h = Clear Interrupt
10PBE10R/W0hPBE10 event
0h = Writing 0 has no effect
1h = Clear Interrupt
9PBE9R/W0hPBE9 event
0h = Writing 0 has no effect
1h = Clear Interrupt
8PBE8R/W0hPBE8 event
0h = Writing 0 has no effect
1h = Clear Interrupt
7PBE7R/W0hPBE7 event
0h = Writing 0 has no effect
1h = Clear Interrupt
6PBE6R/W0hPBE6 event
0h = Writing 0 has no effect
1h = Clear Interrupt
5PBE5R/W0hPBE5 event
0h = Writing 0 has no effect
1h = Clear Interrupt
4PBE4R/W0hPBE4 event
0h = Writing 0 has no effect
1h = Clear Interrupt
3PBE3R/W0hPBE3 event
0h = Writing 0 has no effect
1h = Clear Interrupt
2PBE2R/W0hPBE2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
1PBE1R/W0hPBE1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
0PBE0R/W0hPBE0 event
0h = Writing 0 has no effect
1h = Clear Interrupt

22.5.13 IMASK1 Register (Offset = 84h) [Reset = 00000000h]

IMASK1 is shown in Table 22-15.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 22-15 IMASK1 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30SYSTIM2R/W0hSYSTIM2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
29SYSTIM1R/W0hSYSTIM1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
28SYSTIM0R/W0hSYSTIM0 event
0h = Disable interrupt mask
1h = Enable interrupt mask
27MDMDONER/W0hMDMDONE event
0h = Disable interrupt mask
1h = Enable interrupt mask
26MDMINR/W0hMDMIN event
0h = Disable interrupt mask
1h = Enable interrupt mask
25MDMOUTR/W0hMDMOUT event
0h = Disable interrupt mask
1h = Enable interrupt mask
24MDMSOFT2R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
23MDMSOFT1R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
22MDMSOFT0R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
21RFEDONER/W0hRFEDONE event
0h = Disable interrupt mask
1h = Enable interrupt mask
20RFESOFT1R/W0hRFESOFT1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
19RFESOFT0R/W0hRFESOFT0 event
0h = Disable interrupt mask
1h = Enable interrupt mask
18LOCKR/W0hLOCK event
0h = Disable interrupt mask
1h = Enable interrupt mask
17LOLR/W0hLOSS_OF_LOCK event
0h = Disable interrupt mask
1h = Enable interrupt mask
16TXFIFOR/W0hTXFIFO event
0h = Disable interrupt mask
1h = Enable interrupt mask
15RXFIFOR/W0hRXFIFO event
0h = Disable interrupt mask
1h = Enable interrupt mask
14PBE15R/W0hPBE15 event
0h = Disable interrupt mask
1h = Enable interrupt mask
13PBE14R/W0hPBE14 event
0h = Disable interrupt mask
1h = Enable interrupt mask
12PBE13R/W0hPBE13 event
0h = Disable interrupt mask
1h = Enable interrupt mask
11PBE12R/W0hPBE12 event
0h = Disable interrupt mask
1h = Enable interrupt mask
10PBE11R/W0hPBE11 event
0h = Disable interrupt mask
1h = Enable interrupt mask
9PBE10R/W0hPBE10 event
0h = Disable interrupt mask
1h = Enable interrupt mask
8PBE8R/W0hPBE8 event
0h = Disable interrupt mask
1h = Enable interrupt mask
7PBE7R/W0hPBE7 event
0h = Disable interrupt mask
1h = Enable interrupt mask
6PBE6R/W0hPBE6 event
0h = Disable interrupt mask
1h = Enable interrupt mask
5PBE5R/W0hPBE5 event
0h = Disable interrupt mask
1h = Enable interrupt mask
4PBE4R/W0hPBE4 event
0h = Disable interrupt mask
1h = Enable interrupt mask
3PBE3R/W0hPBE3 event
0h = Disable interrupt mask
1h = Enable interrupt mask
2PBE2R/W0hPBE2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
1PBE1R/W0hPBE1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
0PBE0R/W0hPBE0 event
0h = Disable interrupt mask
1h = Enable interrupt mask

22.5.14 RIS1 Register (Offset = 88h) [Reset = 00000000h]

RIS1 is shown in Table 22-16.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS0 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 22-16 RIS1 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R0hSYSTIM2 event
0h = Interrupt did not occur
1h = Interrupt occurred
30SYSTIM1R0hSYSTIM1 event
0h = Interrupt did not occur
1h = Interrupt occurred
29SYSTIM0R0hSYSTIM0 event
0h = Interrupt did not occur
1h = Interrupt occurred
28MDMDONER0hMDMDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
27MDMINR0hMDMIN event
0h = Interrupt did not occur
1h = Interrupt occurred
26MDMOUTR0hMDMOUT event
0h = Interrupt did not occur
1h = Interrupt occurred
25MDMSOFT2R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
24MDMSOFT1R0hMDMSOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
23MDMSOFT0R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
22RFEDONER0hRFEDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
21RFESOFT1R0hRFESOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
20RFESOFT0R0hRFESOFT0 event
0h = Interrupt did not occur
1h = Interrupt occurred
19LOCKR0hLOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
18LOLR0hLOSS_OF_LOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
17TXFIFOR0hTXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
16RXFIFOR0hRXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
15PBE15R0hPBE15 event
0h = Interrupt did not occur
1h = Interrupt occurred
14PBE14R0hPBE14 event
0h = Interrupt did not occur
1h = Interrupt occurred
13PBE13R0hPBE13 event
0h = Interrupt did not occur
1h = Interrupt occurred
12PBE12R0hPBE12 event
0h = Interrupt did not occur
1h = Interrupt occurred
11PBE11R0hPBE11 event
0h = Interrupt did not occur
1h = Interrupt occurred
10PBE10R0hPBE10 event
0h = Interrupt did not occur
1h = Interrupt occurred
9PBE9R0hPBE9 event
0h = Interrupt did not occur
1h = Interrupt occurred
8PBE8R0hPBE8 event
0h = Interrupt did not occur
1h = Interrupt occurred
7PBE7R0hPBE7 event
0h = Interrupt did not occur
1h = Interrupt occurred
6PBE6R0hPBE6 event
0h = Interrupt did not occur
1h = Interrupt occurred
5PBE5R0hPBE5 event
0h = Interrupt did not occur
1h = Interrupt occurred
4PBE4R0hPBE4 event
0h = Interrupt did not occur
1h = Interrupt occurred
3PBE3R0hPBE3 event
0h = Interrupt did not occur
1h = Interrupt occurred
2PBE2R0hPBE2 event
0h = Interrupt did not occur
1h = Interrupt occurred
1PBE1R0hPBE1 event
0h = Interrupt did not occur
1h = Interrupt occurred
0PBE0R0hPBE0 event
0h = Interrupt did not occur
1h = Interrupt occurred

22.5.15 MIS1 Register (Offset = 8Ch) [Reset = 00000000h]

MIS1 is shown in Table 22-17.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 22-17 MIS1 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R0hSYSTIM2 event
0h = Interrupt did not occur
1h = Interrupt occurred
30SYSTIM1R0hSYSTIM1 event
0h = Interrupt did not occur
1h = Interrupt occurred
29SYSTIM0R0hSYSTIM0 event
0h = Interrupt did not occur
1h = Interrupt occurred
28MDMDONER0hMDMDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
27MDMINR0hMDMIN event
0h = Interrupt did not occur
1h = Interrupt occurred
26MDMOUTR0hMDMOUT event
0h = Interrupt did not occur
1h = Interrupt occurred
25MDMSOFT2R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
24MDMSOFT1R0hMDMSOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
23MDMSOFT0R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
22RFEDONER0hRFEDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
21RFESOFT1R0hRFESOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
20RFESOFT0R0hRFESOFT0 event
0h = Interrupt did not occur
1h = Interrupt occurred
19LOCKR0hLOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
18LOLR0hLOSS_OF_LOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
17TXFIFOR0hTXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
16RXFIFOR0hRXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
15PBE15R0hPBE15 event
0h = Interrupt did not occur
1h = Interrupt occurred
14PBE14R0hPBE14 event
0h = Interrupt did not occur
1h = Interrupt occurred
13PBE13R0hPBE13 event
0h = Interrupt did not occur
1h = Interrupt occurred
12PBE12R0hPBE12 event
0h = Interrupt did not occur
1h = Interrupt occurred
11PBE11R0hPBE11 event
0h = Interrupt did not occur
1h = Interrupt occurred
10PBE10R0hPBE10 event
0h = Interrupt did not occur
1h = Interrupt occurred
9PBE9R0hPBE9 event
0h = Interrupt did not occur
1h = Interrupt occurred
8PBE8R0hPBE8 event
0h = Interrupt did not occur
1h = Interrupt occurred
7PBE7R0hPBE7 event
0h = Interrupt did not occur
1h = Interrupt occurred
6PBE6R0hPBE6 event
0h = Interrupt did not occur
1h = Interrupt occurred
5PBE5R0hPBE5 event
0h = Interrupt did not occur
1h = Interrupt occurred
4PBE4R0hPBE4 event
0h = Interrupt did not occur
1h = Interrupt occurred
3PBE3R0hPBE3 event
0h = Interrupt did not occur
1h = Interrupt occurred
2PBE2R0hPBE2 event
0h = Interrupt did not occur
1h = Interrupt occurred
1PBE1R0hPBE1 event
0h = Interrupt did not occur
1h = Interrupt occurred
0PBE0R0hPBE0 event
0h = Interrupt did not occur
1h = Interrupt occurred

22.5.16 ISET1 Register (Offset = 90h) [Reset = 00000000h]

ISET1 is shown in Table 22-18.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 22-18 ISET1 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Writing 0 has no effect
1h = Set Interrupt
30SYSTIM1R/W0hSYSTIM1 event
0h = Writing 0 has no effect
1h = Set Interrupt
29SYSTIM0R/W0hSYSTIM0 event
0h = Writing 0 has no effect
1h = Set Interrupt
28MDMDONER/W0hMDMDONE event
0h = Writing 0 has no effect
1h = Set Interrupt
27MDMINR/W0hMDMIN event
0h = Writing 0 has no effect
1h = Set Interrupt
26MDMOUTR/W0hMDMOUT event
0h = Writing 0 has no effect
1h = Set Interrupt
25MDMSOFT2R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Set Interrupt
24MDMSOFT1R/W0hMDMSOFT1 event
0h = Writing 0 has no effect
1h = Set Interrupt
23MDMSOFT0R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Set Interrupt
22RFEDONER/W0hRFEDONE event
0h = Writing 0 has no effect
1h = Set Interrupt
21RFESOFT1R/W0hRFESOFT1 event
0h = Writing 0 has no effect
1h = Set Interrupt
20RFESOFT0R/W0hRFESOFT0 event
0h = Writing 0 has no effect
1h = Set Interrupt
19LOCKR/W0hLOCK event
0h = Writing 0 has no effect
1h = Set Interrupt
18LOLR/W0hLOSS_OF_LOCK event
0h = Writing 0 has no effect
1h = Set Interrupt
17TXFIFOR/W0hTXFIFO event
0h = Writing 0 has no effect
1h = Set Interrupt
16RXFIFOR/W0hRXFIFO event
0h = Writing 0 has no effect
1h = Set Interrupt
15PBE15R/W0hPBE15 event
0h = Writing 0 has no effect
1h = Set Interrupt
14PBE14R/W0hPBE14 event
0h = Writing 0 has no effect
1h = Set Interrupt
13PBE13R/W0hPBE13 event
0h = Writing 0 has no effect
1h = Set Interrupt
12PBE12R/W0hPBE12 event
0h = Writing 0 has no effect
1h = Set Interrupt
11PBE11R/W0hPBE11 event
0h = Writing 0 has no effect
1h = Set Interrupt
10PBE10R/W0hPBE10 event
0h = Writing 0 has no effect
1h = Set Interrupt
9PBE9R/W0hPBE9 event
0h = Writing 0 has no effect
1h = Set Interrupt
8PBE8R/W0hPBE8 event
0h = Writing 0 has no effect
1h = Set Interrupt
7PBE7R/W0hPBE7 event
0h = Writing 0 has no effect
1h = Set Interrupt
6PBE6R/W0hPBE6 event
0h = Writing 0 has no effect
1h = Set Interrupt
5PBE5R/W0hPBE5 event
0h = Writing 0 has no effect
1h = Set Interrupt
4PBE4R/W0hPBE4 event
0h = Writing 0 has no effect
1h = Set Interrupt
3PBE3R/W0hPBE3 event
0h = Writing 0 has no effect
1h = Set Interrupt
2PBE2R/W0hPBE2 event
0h = Writing 0 has no effect
1h = Set Interrupt
1PBE1R/W0hPBE1 event
0h = Writing 0 has no effect
1h = Set Interrupt
0PBE0R/W0hPBE0 event
0h = Writing 0 has no effect
1h = Set Interrupt

22.5.17 ICLR1 Register (Offset = 94h) [Reset = 00000000h]

ICLR1 is shown in Table 22-19.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 22-19 ICLR1 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
30SYSTIM1R/W0hSYSTIM1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
29SYSTIM0R/W0hSYSTIM0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
28MDMDONER/W0hMDMDONE event
0h = Writing 0 has no effect
1h = Clear Interrupt
27MDMINR/W0hMDMIN event
0h = Writing 0 has no effect
1h = Clear Interrupt
26MDMOUTR/W0hMDMOUT event
0h = Writing 0 has no effect
1h = Clear Interrupt
25MDMSOFT2R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Clear Interrupt
24MDMSOFT1R/W0hMDMSOFT1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
23MDMSOFT0R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Clear Interrupt
22RFEDONER/W0hRFEDONE event
0h = Writing 0 has no effect
1h = Clear Interrupt
21RFESOFT1R/W0hRFESOFT1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
20RFESOFT0R/W0hRFESOFT0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
19LOCKR/W0hLOCK event
0h = Writing 0 has no effect
1h = Clear Interrupt
18LOLR/W0hLOSS_OF_LOCK event
0h = Writing 0 has no effect
1h = Clear Interrupt
17TXFIFOR/W0hTXFIFO event
0h = Writing 0 has no effect
1h = Clear Interrupt
16RXFIFOR/W0hRXFIFO event
0h = Writing 0 has no effect
1h = Clear Interrupt
15PBE15R/W0hPBE15 event
0h = Writing 0 has no effect
1h = Clear Interrupt
14PBE14R/W0hPBE14 event
0h = Writing 0 has no effect
1h = Clear Interrupt
13PBE13R/W0hPBE13 event
0h = Writing 0 has no effect
1h = Clear Interrupt
12PBE12R/W0hPBE12 event
0h = Writing 0 has no effect
1h = Clear Interrupt
11PBE11R/W0hPBE11 event
0h = Writing 0 has no effect
1h = Clear Interrupt
10PBE10R/W0hPBE10 event
0h = Writing 0 has no effect
1h = Clear Interrupt
9PBE9R/W0hPBE9 event
0h = Writing 0 has no effect
1h = Clear Interrupt
8PBE8R/W0hPBE8 event
0h = Writing 0 has no effect
1h = Clear Interrupt
7PBE7R/W0hPBE7 event
0h = Writing 0 has no effect
1h = Clear Interrupt
6PBE6R/W0hPBE6 event
0h = Writing 0 has no effect
1h = Clear Interrupt
5PBE5R/W0hPBE5 event
0h = Writing 0 has no effect
1h = Clear Interrupt
4PBE4R/W0hPBE4 event
0h = Writing 0 has no effect
1h = Clear Interrupt
3PBE3R/W0hPBE3 event
0h = Writing 0 has no effect
1h = Clear Interrupt
2PBE2R/W0hPBE2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
1PBE1R/W0hPBE1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
0PBE0R/W0hPBE0 event
0h = Writing 0 has no effect
1h = Clear Interrupt

22.5.18 IMASK2 Register (Offset = C4h) [Reset = 00000000h]

IMASK2 is shown in Table 22-20.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 22-20 IMASK2 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30SYSTIM2R/W0hSYSTIM2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
29SYSTIM1R/W0hSYSTIM1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
28SYSTIM0R/W0hSYSTIM0 event
0h = Disable interrupt mask
1h = Enable interrupt mask
27MDMDONER/W0hMDMDONE event
0h = Disable interrupt mask
1h = Enable interrupt mask
26MDMINR/W0hMDMIN event
0h = Disable interrupt mask
1h = Enable interrupt mask
25MDMOUTR/W0hMDMOUT event
0h = Disable interrupt mask
1h = Enable interrupt mask
24MDMSOFT2R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
23MDMSOFT1R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
22MDMSOFT0R/W0hMDMSOFT2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
21RFEDONER/W0hRFEDONE event
0h = Disable interrupt mask
1h = Enable interrupt mask
20RFESOFT1R/W0hRFESOFT1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
19RFESOFT0R/W0hRFESOFT0 event
0h = Disable interrupt mask
1h = Enable interrupt mask
18LOCKR/W0hLOCK event
0h = Disable interrupt mask
1h = Enable interrupt mask
17LOLR/W0hLOSS_OF_LOCK event
0h = Disable interrupt mask
1h = Enable interrupt mask
16TXFIFOR/W0hTXFIFO event
0h = Disable interrupt mask
1h = Enable interrupt mask
15RXFIFOR/W0hRXFIFO event
0h = Disable interrupt mask
1h = Enable interrupt mask
14PBE15R/W0hPBE15 event
0h = Disable interrupt mask
1h = Enable interrupt mask
13PBE14R/W0hPBE14 event
0h = Disable interrupt mask
1h = Enable interrupt mask
12PBE13R/W0hPBE13 event
0h = Disable interrupt mask
1h = Enable interrupt mask
11PBE12R/W0hPBE12 event
0h = Disable interrupt mask
1h = Enable interrupt mask
10PBE11R/W0hPBE11 event
0h = Disable interrupt mask
1h = Enable interrupt mask
9PBE10R/W0hPBE10 event
0h = Disable interrupt mask
1h = Enable interrupt mask
8PBE8R/W0hPBE8 event
0h = Disable interrupt mask
1h = Enable interrupt mask
7PBE7R/W0hPBE7 event
0h = Disable interrupt mask
1h = Enable interrupt mask
6PBE6R/W0hPBE6 event
0h = Disable interrupt mask
1h = Enable interrupt mask
5PBE5R/W0hPBE5 event
0h = Disable interrupt mask
1h = Enable interrupt mask
4PBE4R/W0hPBE4 event
0h = Disable interrupt mask
1h = Enable interrupt mask
3PBE3R/W0hPBE3 event
0h = Disable interrupt mask
1h = Enable interrupt mask
2PBE2R/W0hPBE2 event
0h = Disable interrupt mask
1h = Enable interrupt mask
1PBE1R/W0hPBE1 event
0h = Disable interrupt mask
1h = Enable interrupt mask
0PBE0R/W0hPBE0 event
0h = Disable interrupt mask
1h = Enable interrupt mask

22.5.19 RIS2 Register (Offset = C8h) [Reset = 00000000h]

RIS2 is shown in Table 22-21.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS0 register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Table 22-21 RIS2 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R0hSYSTIM2 event
0h = Interrupt did not occur
1h = Interrupt occurred
30SYSTIM1R0hSYSTIM1 event
0h = Interrupt did not occur
1h = Interrupt occurred
29SYSTIM0R0hSYSTIM0 event
0h = Interrupt did not occur
1h = Interrupt occurred
28MDMDONER0hMDMDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
27MDMINR0hMDMIN event
0h = Interrupt did not occur
1h = Interrupt occurred
26MDMOUTR0hMDMOUT event
0h = Interrupt did not occur
1h = Interrupt occurred
25MDMSOFT2R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
24MDMSOFT1R0hMDMSOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
23MDMSOFT0R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
22RFEDONER0hRFEDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
21RFESOFT1R0hRFESOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
20RFESOFT0R0hRFESOFT0 event
0h = Interrupt did not occur
1h = Interrupt occurred
19LOCKR0hLOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
18LOLR0hLOSS_OF_LOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
17TXFIFOR0hTXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
16RXFIFOR0hRXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
15PBE15R0hPBE15 event
0h = Interrupt did not occur
1h = Interrupt occurred
14PBE14R0hPBE14 event
0h = Interrupt did not occur
1h = Interrupt occurred
13PBE13R0hPBE13 event
0h = Interrupt did not occur
1h = Interrupt occurred
12PBE12R0hPBE12 event
0h = Interrupt did not occur
1h = Interrupt occurred
11PBE11R0hPBE11 event
0h = Interrupt did not occur
1h = Interrupt occurred
10PBE10R0hPBE10 event
0h = Interrupt did not occur
1h = Interrupt occurred
9PBE9R0hPBE9 event
0h = Interrupt did not occur
1h = Interrupt occurred
8PBE8R0hPBE8 event
0h = Interrupt did not occur
1h = Interrupt occurred
7PBE7R0hPBE7 event
0h = Interrupt did not occur
1h = Interrupt occurred
6PBE6R0hPBE6 event
0h = Interrupt did not occur
1h = Interrupt occurred
5PBE5R0hPBE5 event
0h = Interrupt did not occur
1h = Interrupt occurred
4PBE4R0hPBE4 event
0h = Interrupt did not occur
1h = Interrupt occurred
3PBE3R0hPBE3 event
0h = Interrupt did not occur
1h = Interrupt occurred
2PBE2R0hPBE2 event
0h = Interrupt did not occur
1h = Interrupt occurred
1PBE1R0hPBE1 event
0h = Interrupt did not occur
1h = Interrupt occurred
0PBE0R0hPBE0 event
0h = Interrupt did not occur
1h = Interrupt occurred

22.5.20 MIS2 Register (Offset = CCh) [Reset = 00000000h]

MIS2 is shown in Table 22-22.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Table 22-22 MIS2 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R0hSYSTIM2 event
0h = Interrupt did not occur
1h = Interrupt occurred
30SYSTIM1R0hSYSTIM1 event
0h = Interrupt did not occur
1h = Interrupt occurred
29SYSTIM0R0hSYSTIM0 event
0h = Interrupt did not occur
1h = Interrupt occurred
28MDMDONER0hMDMDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
27MDMINR0hMDMIN event
0h = Interrupt did not occur
1h = Interrupt occurred
26MDMOUTR0hMDMOUT event
0h = Interrupt did not occur
1h = Interrupt occurred
25MDMSOFT2R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
24MDMSOFT1R0hMDMSOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
23MDMSOFT0R0hMDMSOFT event
0h = Interrupt did not occur
1h = Interrupt occurred
22RFEDONER0hRFEDONE event
0h = Interrupt did not occur
1h = Interrupt occurred
21RFESOFT1R0hRFESOFT1 event
0h = Interrupt did not occur
1h = Interrupt occurred
20RFESOFT0R0hRFESOFT0 event
0h = Interrupt did not occur
1h = Interrupt occurred
19LOCKR0hLOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
18LOLR0hLOSS_OF_LOCK event
0h = Interrupt did not occur
1h = Interrupt occurred
17TXFIFOR0hTXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
16RXFIFOR0hRXFIFO event
0h = Interrupt did not occur
1h = Interrupt occurred
15PBE15R0hPBE15 event
0h = Interrupt did not occur
1h = Interrupt occurred
14PBE14R0hPBE14 event
0h = Interrupt did not occur
1h = Interrupt occurred
13PBE13R0hPBE13 event
0h = Interrupt did not occur
1h = Interrupt occurred
12PBE12R0hPBE12 event
0h = Interrupt did not occur
1h = Interrupt occurred
11PBE11R0hPBE11 event
0h = Interrupt did not occur
1h = Interrupt occurred
10PBE10R0hPBE10 event
0h = Interrupt did not occur
1h = Interrupt occurred
9PBE9R0hPBE9 event
0h = Interrupt did not occur
1h = Interrupt occurred
8PBE8R0hPBE8 event
0h = Interrupt did not occur
1h = Interrupt occurred
7PBE7R0hPBE7 event
0h = Interrupt did not occur
1h = Interrupt occurred
6PBE6R0hPBE6 event
0h = Interrupt did not occur
1h = Interrupt occurred
5PBE5R0hPBE5 event
0h = Interrupt did not occur
1h = Interrupt occurred
4PBE4R0hPBE4 event
0h = Interrupt did not occur
1h = Interrupt occurred
3PBE3R0hPBE3 event
0h = Interrupt did not occur
1h = Interrupt occurred
2PBE2R0hPBE2 event
0h = Interrupt did not occur
1h = Interrupt occurred
1PBE1R0hPBE1 event
0h = Interrupt did not occur
1h = Interrupt occurred
0PBE0R0hPBE0 event
0h = Interrupt did not occur
1h = Interrupt occurred

22.5.21 ISET2 Register (Offset = D0h) [Reset = 00000000h]

ISET2 is shown in Table 22-23.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 22-23 ISET2 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Writing 0 has no effect
1h = Set Interrupt
30SYSTIM1R/W0hSYSTIM1 event
0h = Writing 0 has no effect
1h = Set Interrupt
29SYSTIM0R/W0hSYSTIM0 event
0h = Writing 0 has no effect
1h = Set Interrupt
28MDMDONER/W0hMDMDONE event
0h = Writing 0 has no effect
1h = Set Interrupt
27MDMINR/W0hMDMIN event
0h = Writing 0 has no effect
1h = Set Interrupt
26MDMOUTR/W0hMDMOUT event
0h = Writing 0 has no effect
1h = Set Interrupt
25MDMSOFT2R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Set Interrupt
24MDMSOFT1R/W0hMDMSOFT1 event
0h = Writing 0 has no effect
1h = Set Interrupt
23MDMSOFT0R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Set Interrupt
22RFEDONER/W0hRFEDONE event
0h = Writing 0 has no effect
1h = Set Interrupt
21RFESOFT1R/W0hRFESOFT1 event
0h = Writing 0 has no effect
1h = Set Interrupt
20RFESOFT0R/W0hRFESOFT0 event
0h = Writing 0 has no effect
1h = Set Interrupt
19LOCKR/W0hLOCK event
0h = Writing 0 has no effect
1h = Set Interrupt
18LOLR/W0hLOSS_OF_LOCK event
0h = Writing 0 has no effect
1h = Set Interrupt
17TXFIFOR/W0hTXFIFO event
0h = Writing 0 has no effect
1h = Set Interrupt
16RXFIFOR/W0hRXFIFO event
0h = Writing 0 has no effect
1h = Set Interrupt
15PBE15R/W0hPBE15 event
0h = Writing 0 has no effect
1h = Set Interrupt
14PBE14R/W0hPBE14 event
0h = Writing 0 has no effect
1h = Set Interrupt
13PBE13R/W0hPBE13 event
0h = Writing 0 has no effect
1h = Set Interrupt
12PBE12R/W0hPBE12 event
0h = Writing 0 has no effect
1h = Set Interrupt
11PBE11R/W0hPBE11 event
0h = Writing 0 has no effect
1h = Set Interrupt
10PBE10R/W0hPBE10 event
0h = Writing 0 has no effect
1h = Set Interrupt
9PBE9R/W0hPBE9 event
0h = Writing 0 has no effect
1h = Set Interrupt
8PBE8R/W0hPBE8 event
0h = Writing 0 has no effect
1h = Set Interrupt
7PBE7R/W0hPBE7 event
0h = Writing 0 has no effect
1h = Set Interrupt
6PBE6R/W0hPBE6 event
0h = Writing 0 has no effect
1h = Set Interrupt
5PBE5R/W0hPBE5 event
0h = Writing 0 has no effect
1h = Set Interrupt
4PBE4R/W0hPBE4 event
0h = Writing 0 has no effect
1h = Set Interrupt
3PBE3R/W0hPBE3 event
0h = Writing 0 has no effect
1h = Set Interrupt
2PBE2R/W0hPBE2 event
0h = Writing 0 has no effect
1h = Set Interrupt
1PBE1R/W0hPBE1 event
0h = Writing 0 has no effect
1h = Set Interrupt
0PBE0R/W0hPBE0 event
0h = Writing 0 has no effect
1h = Set Interrupt

22.5.22 ICLR2 Register (Offset = D4h) [Reset = 00000000h]

ICLR2 is shown in Table 22-24.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Table 22-24 ICLR2 Register Field Descriptions
BitFieldTypeResetDescription
31SYSTIM2R/W0hSYSTIM2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
30SYSTIM1R/W0hSYSTIM1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
29SYSTIM0R/W0hSYSTIM0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
28MDMDONER/W0hMDMDONE event
0h = Writing 0 has no effect
1h = Clear Interrupt
27MDMINR/W0hMDMIN event
0h = Writing 0 has no effect
1h = Clear Interrupt
26MDMOUTR/W0hMDMOUT event
0h = Writing 0 has no effect
1h = Clear Interrupt
25MDMSOFT2R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Clear Interrupt
24MDMSOFT1R/W0hMDMSOFT1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
23MDMSOFT0R/W0hMDMSOFT event
0h = Writing 0 has no effect
1h = Clear Interrupt
22RFEDONER/W0hRFEDONE event
0h = Writing 0 has no effect
1h = Clear Interrupt
21RFESOFT1R/W0hRFESOFT1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
20RFESOFT0R/W0hRFESOFT0 event
0h = Writing 0 has no effect
1h = Clear Interrupt
19LOCKR/W0hLOCK event
0h = Writing 0 has no effect
1h = Clear Interrupt
18LOLR/W0hLOSS_OF_LOCK event
0h = Writing 0 has no effect
1h = Clear Interrupt
17TXFIFOR/W0hTXFIFO event
0h = Writing 0 has no effect
1h = Clear Interrupt
16RXFIFOR/W0hRXFIFO event
0h = Writing 0 has no effect
1h = Clear Interrupt
15PBE15R/W0hPBE15 event
0h = Writing 0 has no effect
1h = Clear Interrupt
14PBE14R/W0hPBE14 event
0h = Writing 0 has no effect
1h = Clear Interrupt
13PBE13R/W0hPBE13 event
0h = Writing 0 has no effect
1h = Clear Interrupt
12PBE12R/W0hPBE12 event
0h = Writing 0 has no effect
1h = Clear Interrupt
11PBE11R/W0hPBE11 event
0h = Writing 0 has no effect
1h = Clear Interrupt
10PBE10R/W0hPBE10 event
0h = Writing 0 has no effect
1h = Clear Interrupt
9PBE9R/W0hPBE9 event
0h = Writing 0 has no effect
1h = Clear Interrupt
8PBE8R/W0hPBE8 event
0h = Writing 0 has no effect
1h = Clear Interrupt
7PBE7R/W0hPBE7 event
0h = Writing 0 has no effect
1h = Clear Interrupt
6PBE6R/W0hPBE6 event
0h = Writing 0 has no effect
1h = Clear Interrupt
5PBE5R/W0hPBE5 event
0h = Writing 0 has no effect
1h = Clear Interrupt
4PBE4R/W0hPBE4 event
0h = Writing 0 has no effect
1h = Clear Interrupt
3PBE3R/W0hPBE3 event
0h = Writing 0 has no effect
1h = Clear Interrupt
2PBE2R/W0hPBE2 event
0h = Writing 0 has no effect
1h = Clear Interrupt
1PBE1R/W0hPBE1 event
0h = Writing 0 has no effect
1h = Clear Interrupt
0PBE0R/W0hPBE0 event
0h = Writing 0 has no effect
1h = Clear Interrupt