SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 7-3 lists the memory-mapped registers for the VIMS registers. All register offset addresses not listed in Table 7-3 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DESC | Module Description | Go |
4h | DESCEX | Extended Module Description | Go |
8h | FLWS1T | Internal. Only to be used through TI provided API. | Go |
Ch | FLWS2T | Internal. Only to be used through TI provided API. | Go |
18h | PTRMC0 | Internal. Only to be used through TI provided API. | Go |
1Ch | B0TRMC1 | Internal. Only to be used through TI provided API. | Go |
20h | B0TRMC0 | Internal. Only to be used through TI provided API. | Go |
100h | FLBLCK | Internal. Only to be used through TI provided API. | Go |
3FCh | CFG | Internal. Only to be used through TI provided API. | Go |
410h | WEPRA | Flash main region write/erase protection configuration 1 | Go |
414h | WEPRB | Flash main region write/erase protection configuration 2 | Go |
41Ch | WEPRAUX | Flash write/erase protection configuration for other regions | Go |
420h | FLBSTAT | Flash status | Go |
424h | CCHCTRL | Cache control | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-4 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DESC is shown in Table 7-5.
Return to the Summary Table.
Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | D140h | Module identifier used to uniquely identify this IP. |
15-12 | STDIPOFF | R | 0h | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
11-8 | INSTIDX | R | 0h | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). |
7-4 | MAJREV | R | 1h | Major revision of IP (0-15). |
3-0 | MINREV | R | 0h | Minor revision of IP (0-15). |
DESCEX is shown in Table 7-6.
Return to the Summary Table.
Extended Description Register. This register provides configuration details of the IP to software drivers and end users.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27 | NBANK | R | 1h | Provides the FLASH Bank count |
26-15 | FLSZ | R | 1FFh | This provides the total FLASH size in Kilo Bytes. The total FLASH size is (FLSZ + 1)KB |
14-0 | ROMSZ | R | 3000h | Provides the size of ROM in Bytes. |
FLWS1T is shown in Table 7-7.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | VAL | R/W | 7h | Internal. Only to be used through TI provided API. |
FLWS2T is shown in Table 7-8.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | VAL | R/W | 7h | Internal. Only to be used through TI provided API. |
PTRMC0 is shown in Table 7-9.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 131A0000h | Internal. Only to be used through TI provided API. |
B0TRMC1 is shown in Table 7-10.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Internal. Only to be used through TI provided API. |
B0TRMC0 is shown in Table 7-11.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Internal. Only to be used through TI provided API. |
FLBLCK is shown in Table 7-12.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R/W | 0h | Internal. Only to be used through TI provided API. |
CFG is shown in Table 7-13.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | Reserved |
1 | TRMVLID | R/W | 0h | Internal. Only to be used through TI provided API. |
0 | WEPRTRM | R/W | 1h | Internal. Only to be used through TI provided API. |
WEPRA is shown in Table 7-14.
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Flash main region write/erase protection for first 32 sectors. Nth bit corresponds to the Nth sector. This register is sticky when written with value 0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | Flash write/erase protection configuration value. |
WEPRB is shown in Table 7-15.
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Flash main region write/erase protection for remaining sectors. Each bit corresponds to 8 sectors. Bit 0 corresponds to sector 32-39, bit 1 corresponds to sector 40-47 and so on. This register is sticky when written with value 0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-0 | VAL | R/W | 0FFFFFFFh | Flash write/erase protection configuration value. |
WEPRAUX is shown in Table 7-16.
Return to the Summary Table.
Flash Write/Erase protection for Non-Main, TRIM and ENGR Regions. This register is sticky when written with value 0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | WEPREGR | R/W | 1h | Flash engr region write/erase protection configuration value. |
1 | WEPRTRM | R/W | 1h | Flash trim region write/erase protection configuration value. |
0 | WEPRNMN | R/W | 1h | Flash non main region write/erase protection configuration value. |
FLBSTAT is shown in Table 7-17.
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This register is used to indicate status of flash. This register is not retained.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | PARERR | R | 0h | This bit indicates parity error on write/erase and read protection MMRs. This bit is sticky when set to 1 by hardware.
0h = No Error 1h = Error |
2 | B0BSY | R | 0h | This bit indicates if flash is busy.
0h = Idle 1h = Busy |
1 | B2TRDY | R | 0h | This bit indicates if flash is ready in 2T mode.
0h = Not Ready 1h = Ready |
0 | B1TRDY | R | 0h | This bit indicates if flash is ready in 1T mode.
0h = Not Ready 1h = Ready |
CCHCTRL is shown in Table 7-18.
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This register is used for enabling cache, prefetch and micropredictor units.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | CCHMPEN | R/W | 1h | This bit is used to enable the micropredictor unit.
0h = Disable 1h = Enable |
1 | CCHPFEN | R/W | 1h | This bit is used to enable the prefetch unit.
0h = Disable 1h = Enable |
0 | CCHEN | R/W | 1h | This bit is used to enable the cache.
0h = Disable 1h = Enable |