SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

6.9 CKMD Registers

Table 6-4 lists the memory-mapped registers for the CKMD registers. All register offset addresses not listed in Table 6-4 should be considered as reserved locations and the register contents should not be modified.

Table 6-4 CKMD Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register.Go
44hIMASKInterrupt mask.Go
48hRISRaw interrupt status.Go
4ChMISMasked interrupt status.Go
50hISETInterrupt set register.Go
54hICLRInterrupt clear register.Go
58hIMSETInterrupt mask set register.Go
5ChIMCLRInterrupt mask clear register.Go
80hHFOSCCTLInternal. Only to be used through TI provided API.Go
84hHFXTCTLHigh frequency crystal controlGo
8ChLFOSCCTLLow frequency oscillator controlGo
90hLFXTCTLLow frequency crystal controlGo
94hLFQUALCTLLow frequency clock qualification controlGo
98hLFINCCTLLow frequency time increment controlGo
9ChLFINCOVRLow frequency time increment override controlGo
A0hAMPADCCTLInternal. Only to be used through TI provided API.Go
A4hHFTRACKCTLHigh frequency tracking loop controlGo
A8hLDOCTLInternal. Only to be used through TI provided API.Go
AChNABIASCTLNanoamp-bias controlGo
B0hLFMONCTLLow-frequency clock-monitor controlGo
C0hLFCLKSELLow frequency clock selectionGo
C4hTDCCLKSELInternal. Only to be used through TI provided API.Go
C8hADCCLKSELADC clock selectionGo
E0hLFCLKSTATLow-frequency clock statusGo
E4hHFXTSTATHFXT status informationGo
E8hAMPADCSTATInternal. Only to be used through TI provided API.Go
EChTRACKSTATHFOSC tracking loop status informationGo
F0hAMPSTATHFXT Amplitude Compensation StatusGo
100hATBCTL0Internal. Only to be used through TI provided API.Go
104hATBCTL1Internal. Only to be used through TI provided API.Go
108hDTBCTLDigital test bus mux controlGo
110hTRIM0Internal. Only to be used through TI provided API.Go
114hTRIM1Internal. Only to be used through TI provided API.Go
118hHFXTINITInitial values for HFXT rampingGo
11ChHFXTTARGTarget values for HFXT rampingGo
120hHFXTDYNAlternative target values for HFXT configurationGo
124hAMPCFG0Amplitude Compensation Configuration 0Go
128hAMPCFG1Amplitude Compensation Configuration 1Go
12ChLOOPCFGConfiguration Register for the Tracking LoopGo
200hTDCCTLInternal. Only to be used through TI provided API.Go
204hTDCSTATInternal. Only to be used through TI provided API.Go
208hTDCRESULTInternal. Only to be used through TI provided API.Go
20ChTDCSATCFGInternal. Only to be used through TI provided API.Go
210hTDCTRIGSRCInternal. Only to be used through TI provided API.Go
214hTDCTRIGCNTInternal. Only to be used through TI provided API.Go
218hTDCTRIGCNTLOADInternal. Only to be used through TI provided API.Go
21ChTDCTRIGCNTCFGInternal. Only to be used through TI provided API.Go
220hTDCPRECTLInternal. Only to be used through TI provided API.Go
224hTDCPRECNTRInternal. Only to be used through TI provided API.Go
300hWDTCNTWDT counter value registerGo
304hWDTTESTWDT test mode registerGo
308hWDTLOCKWDT lock registerGo

Complex bit access types are encoded to fit into small table cells. Table 6-5 shows the codes that are used for access types in this section.

Table 6-5 CKMD Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.9.1 DESC Register (Offset = 0h) [Reset = 9B4B1000h]

DESC is shown in Table 6-6.

Return to the Summary Table.

Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 6-6 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR9B4BhModule identifier used to uniquely identify this IP.
15-12STDIPOFFR1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
NOTE: This IP does not have DTB as part of the Standard IP MMRs. It uses DTBCTL instead.
11-8RESERVEDR0hReserved
7-4MAJREVR0hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

6.9.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 6-7.

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Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 6-7 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKR/W0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTR/W0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDR/W0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGR/W0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGER/W0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSR/W0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORR/W0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODR/W0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDR/W0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONER/W0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDR/W0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDR/W0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDR/W0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORR/W0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSR/W0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODR/W0hHFXT amplitude good indication.
1HFXTFAULTR/W0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODR/W0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.3 RIS Register (Offset = 48h) [Reset = 00000000h]

RIS is shown in Table 6-8.

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Raw interrupt status.
This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 6-8 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKR0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTR0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDR0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGR0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGER0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSR0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORR0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODR0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDR0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONER0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDR0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDR0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDR0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORR0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSR0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODR0hHFXT amplitude good indication.
1HFXTFAULTR0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODR0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.4 MIS Register (Offset = 4Ch) [Reset = 00000000h]

MIS is shown in Table 6-9.

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Masked interrupt status.
This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 6-9 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKR0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTR0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDR0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGR0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGER0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSR0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORR0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODR0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDR0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONER0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDR0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDR0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDR0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORR0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSR0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODR0hHFXT amplitude good indication.
1HFXTFAULTR0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODR0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.5 ISET Register (Offset = 50h) [Reset = 00000000h]

ISET is shown in Table 6-10.

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Interrupt set register.
This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 6-10 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG.Q1CAP, HFXTTARG.Q2CAP and HFXTTARG.IREF or HFXTDYN.Q1CAP, HFXTDYN.Q2CAP and HFXTDYN.IREF are reached.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.6 ICLR Register (Offset = 54h) [Reset = 00000000h]

ICLR is shown in Table 6-11.

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Interrupt clear register.
This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 6-11 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.7 IMSET Register (Offset = 58h) [Reset = 00000000h]

IMSET is shown in Table 6-12.

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Interrupt mask set register.
Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 6-12 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.8 IMCLR Register (Offset = 5Ch) [Reset = 00000000h]

IMCLR is shown in Table 6-13.

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Interrupt mask clear register.
Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 6-13 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17LFTICKW0h32kHz TICK to RTC and WDT.
Either derived from selected LFCLK or generated from CLKULL in absence of LFCLK.
16LFGEARRSTRTW0hLFINC filter gearing restart.
Indicates that the LFINC filter restarted gearing. Subsequent LFINC estimates may have higher variation.
15AMPSETTLEDW0hHFXT Amplitude compensation - settled
Indicates that the amplitude compensation FSM has reached the SETTLED or TCXOMODE state,
and the controls configured in HFXTTARG or HFXTDYN are reached.
14AMPCTRLATTARGW0hHFXT Amplitude compensation - controls at target
Indicates that the control values configured in HFXTTARG or HFXTDYN are reached.
Applies to Q1CAP, Q2CAP and IREF.
13PRELFEDGEW0hPre-LF clock edge detect.
Indicates that a positive edge occured on the selected pre-LF clock LFCLKSEL.PRE.
Can be used by software to confirm that a LF clock source is running and within the expected frequency,
before selecting it as the main LF clock source.
12LFCLKLOSSW0hLF clock is lost.
Indicates that no LF clock edge occured for ~49us (~1.6 times nominal period).
The system will automatically fall-back to generating LFTICK based on CLKULL,
to avoid timing corruption.
Note that this signal is NOT related to the analog LF clock-loss detector which can reset the device during STANDBY.
11LFCLKOORW0hLF clock period out-of-range.
Indicates that a LF clock period was measured to be out-of-range,
according to LFQUALCTL.MAXERR.
10LFCLKGOODW0hLF clock good.
Indicates that the LF clock is good, according to the configuration in LFQUALCTL.
9LFINCUPDW0hLFINC updated.
Indicates that a new LFINC measurement value is available in LFCLKSTAT.LFINC.
8TDCDONEW0hTDC done event.
Indicates that the TDC measurement is done.
7ADCPEAKUPDW0hHFXT-ADC PEAK measurement update event.
Indicates that the HFXT-ADC PEAK measurement is done.
6ADCBIASUPDW0hHFXT-ADC BIAS measurement update event.
Indicates that the HFXT-ADC BIAS measurement is done.
5ADCCOMPUPDW0hHFXT-ADC comparison update event.
Indicates that the HFXT-ADC comparison is done.
4TRACKREFOORW0hOut-of-range indication from the tracking loop.
Indicates that the selected reference clock frequency of the tracking loop is out-of-range.
3TRACKREFLOSSW0hClock loss indication from the tracking loop.
Indicates that the selected reference clock of the tracking loop is lost.
2HFXTAMPGOODW0hHFXT amplitude good indication.
1HFXTFAULTW0hHFXT fault indication.
Indicates that HFXT did not start correctly, or its frequency is too low.
HFXT will not recover from this fault and has to be restarted.
This is only a one-time check at HFXT startup.
0HFXTGOODW0hHFXT good indication.
Indicates that HFXT started correctly. The frequency is not necessarily good enough for radio operation.
This is only a one-time check at HFXT startup.

6.9.9 HFOSCCTL Register (Offset = 80h) [Reset = 00000000h]

HFOSCCTL is shown in Table 6-14.

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Internal. Only to be used through TI provided API.

Table 6-14 HFOSCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-24PWW0hInternal. Only to be used through TI provided API.
23-9RESERVEDR0hReserved
8CLKSVTOVRR/W0hInternal. Only to be used through TI provided API.
7-2RESERVEDR0hReserved
1FORCEOFFR/W0hInternal. Only to be used through TI provided API.
0QUALBYPR/W0hInternal. Only to be used through TI provided API.

6.9.10 HFXTCTL Register (Offset = 84h) [Reset = 00000000h]

HFXTCTL is shown in Table 6-15.

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High frequency crystal control

Table 6-15 HFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31AMPOVRR/W0hInternal. Only to be used through TI provided API.
30-27RESERVEDR0hReserved
26BIASENR/W0hInternal. Only to be used through TI provided API.
25LPBUFENR/W0hInternal. Only to be used through TI provided API.
24INJECTR/W0hInternal. Only to be used through TI provided API.
23QUALBYPR/W0hInternal. Only to be used through TI provided API.
22-20RESERVEDR0hReserved
19-8QUALDLYR/W0hSkip potentially unstable clock cycles after enabling HFXT.
Number of cycles skipped is 8*QUALDLY.
7TCXOMODER/W0hTemperature compensated crystal oscillator mode.
Set this bit if a TXCO is connected.
6TCXOTYPER/W0hType of temperature compensated crystal used.
Only has effect if TCXOMODE is set.
0h = Use with clipped-sine TCXO
1h = Use with CMOS TCXO
5-3RESERVEDR0hReserved
2AUTOENR/W0hInternal. Only to be used through TI provided API.
1HPBUFENR/W0hHigh performance clock buffer enable.
This bit controls the clock output for the RF PLL.
It is required for radio operation.
0ENR/W0hInternal. Only to be used through TI provided API.

6.9.11 LFOSCCTL Register (Offset = 8Ch) [Reset = 00000000h]

LFOSCCTL is shown in Table 6-16.

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Low frequency oscillator control

Table 6-16 LFOSCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hLFOSC enable

6.9.12 LFXTCTL Register (Offset = 90h) [Reset = 00000000h]

LFXTCTL is shown in Table 6-17.

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Low frequency crystal control

Table 6-17 LFXTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-13LEAKCOMPR/W0hLeakage compensation control
0h = Full leakage compensation
1h = Half leakage compensation
3h = No leakage compensation
12BUFBIASR/W0hControl the BIAS current of the input amp in LP buffer
0h = Minimum bias current: 25nA
1h = Maximum bias current: 50nA
11-8AMPBIASR/W0hAdjust current mirror ratio into oscillator core. This value is depending on crystal and is set by FW. This field uses a 2's complement encoding.
7-6BIASBOOSTR/W0hBoost oscillator amplitude
This value depends on the crystal and needs to be configured by Firmware.
5-4REGBIASR/W0hRegulation loop bias resistor value
This value depends on the crystal and needs to be configured by Firmware.
3RESERVEDR0hReserved
2HPBUFENR/W0hControl the buffer used. In normal operation, low-power buffer is used in all device modes. The high-performance buffer is only used for test purposes.
1AMPREGMODER/W0hAmplitude regulation mode
0h = Amplitude control loop enabled
1h = Amplitude control loop disabled
0ENR/W0hLFXT enable

6.9.13 LFQUALCTL Register (Offset = 94h) [Reset = 00002064h]

LFQUALCTL is shown in Table 6-18.

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Low frequency clock qualification control

Table 6-18 LFQUALCTL Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-8MAXERRR/W20hMaximum LFCLK period error.
Value given in microseconds, 3 integer bits + 3 fractional bits.
7-0CONSECR/W64hNumber of consecutive times the LFCLK period error has to be
smaller than MAXERR to be considered "good".
Setting this value to 0 will bypass clock qualification,
and the "good" indicator will always be 1.

6.9.14 LFINCCTL Register (Offset = 98h) [Reset = 9E848014h]

LFINCCTL is shown in Table 6-19.

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Low frequency time increment control

Table 6-19 LFINCCTL Register Field Descriptions
BitFieldTypeResetDescription
31PREVENTSTBYR/W1hControls if the LFINC filter prevents STANBY entry until settled.
0h = Disable. Do not prevent STANDBY entry.
1h = Enable. Prevent STANDBY entry.
30RESERVEDR0hReserved
29-8INTR/W001E8480hIntegral part of the LFINC filter.
This value is updated by Hardware to reflect the current state of the filter.
It can also be written to change the current state.
7STOPGEARR/W0hControls the final gear of the LFINC filter.
0h = Lowest final gear. Best settling, but less dynamic frequency tracking.
1h = Highest final gear. Best dynamic frequency tracking, but higher variation in filter value.
6-5ERRTHRR/W0hControls the threshold for gearing restart of the LFINC filter.
Only effective if GEARRSTRT is not ONETHR or TWOTHR.
0h = Restart gearing on large error. Fewer false restarts, slower response on small frequency shifts.
1h = Middle value towards LARGE.
2h = Middle value towards SMALL.
3h = Restart gearing on small error. Potentially more false restarts, faster response on small frequency shifts.
4-3GEARRSTRTR/W2hControls gearing restart of the LFINC filter.
0h = Never restart gearing. Very stable filter value, but very slow response on frequency changes.
1h = Restart gearing when the error accumulator crosses the threshold once.
2h = Restart gearing when the error accumulator crosses the threshold twice in a row.
2SOFTRSTRTR/W1hUse a higher gear after re-enabling / wakeup.
The filter will require 16-24 LFCLK periods to settle (depending on STOPGEAR), but may respond faster to frequency changes during STANDBY.
0h = Don't use soft gearing restarts
1h = Use soft gearing restarts
1-0RESERVEDR0hReserved

6.9.15 LFINCOVR Register (Offset = 9Ch) [Reset = 00000000h]

LFINCOVR is shown in Table 6-20.

Return to the Summary Table.

Low frequency time increment override control

Table 6-20 LFINCOVR Register Field Descriptions
BitFieldTypeResetDescription
31OVERRIDER/W0hOverride LF increment
Use the value provided in LFINC instead of the value calculated by Hardware.
30-22RESERVEDR0hReserved
21-0LFINCR/W0hLF increment value
This value is used when OVERRIDE is set to 1.
Otherwise the value is calculated automatically.

6.9.16 AMPADCCTL Register (Offset = A0h) [Reset = 00000000h]

AMPADCCTL is shown in Table 6-21.

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Internal. Only to be used through TI provided API.

Table 6-21 AMPADCCTL Register Field Descriptions
BitFieldTypeResetDescription
31SWOVRR/W0hInternal. Only to be used through TI provided API.
30-18RESERVEDR0hReserved
17PEAKDETENR/W0hInternal. Only to be used through TI provided API.
16ADCENR/W0hInternal. Only to be used through TI provided API.
15RESERVEDR0hReserved
14-8COMPVALR/W0hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4SRCSELR/W0hInternal. Only to be used through TI provided API.
3-2RESERVEDR0hReserved
1COMPSTRTR/W0hInternal. Only to be used through TI provided API.
0SARSTRTR/W0hInternal. Only to be used through TI provided API.

6.9.17 HFTRACKCTL Register (Offset = A4h) [Reset = 00400000h]

HFTRACKCTL is shown in Table 6-22.

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High frequency tracking loop control

Table 6-22 HFTRACKCTL Register Field Descriptions
BitFieldTypeResetDescription
31ENR/W0hEnable tracking loop.
30DSMBYPR/W0hBypass Delta-Sigma-Modulation of fine trim.
29-28RESERVEDR0hReserved
27-26REFCLKR/W0hSelect the reference clock for the tracking loop.
Change only while the tracking loop is disabled.
0h = Select HFXT as reference clock.
1h = Select LRF reference clock.
2h = Select GPI as reference clock.
25-0RATIOR/W00400000hReference clock ratio.
RATIO = 24MHz / (2*reference-frequency) * 224
Commonly used reference clock frequencies are provided as enumerations.
00400000h = Use for 48MHz reference clock
01800000h = Use for 8MHz reference clock
03000000h = Use for 4MHz reference clock

6.9.18 LDOCTL Register (Offset = A8h) [Reset = 00000000h]

LDOCTL is shown in Table 6-23.

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Internal. Only to be used through TI provided API.

Table 6-23 LDOCTL Register Field Descriptions
BitFieldTypeResetDescription
31SWOVRR/W0hInternal. Only to be used through TI provided API.
30-5RESERVEDR0hReserved
4HFXTLVLENR/W0hInternal. Only to be used through TI provided API.
3STARTCTLR/W0hInternal. Only to be used through TI provided API.
2STARTR/W0hInternal. Only to be used through TI provided API.
1BYPASSR/W0hInternal. Only to be used through TI provided API.
0ENR/W0hInternal. Only to be used through TI provided API.

6.9.19 NABIASCTL Register (Offset = ACh) [Reset = 00000000h]

NABIASCTL is shown in Table 6-24.

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Nanoamp-bias control

Table 6-24 NABIASCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hEnable nanoamp-bias

6.9.20 LFMONCTL Register (Offset = B0h) [Reset = 00000000h]

LFMONCTL is shown in Table 6-25.

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Low-frequency clock-monitor control

Table 6-25 LFMONCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hEnable LFMONITOR.
Enable only after a LF clock source has been selected, enabled and is stable.
If LFMONITOR detects a clock loss, the system will be reset.

6.9.21 LFCLKSEL Register (Offset = C0h) [Reset = 00000000h]

LFCLKSEL is shown in Table 6-26.

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Low frequency clock selection

Table 6-26 LFCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-2PRER/W0hSelect low frequency clock source for the PRELFCLK interrupt.
Can be used by Software to confirm that the clock is running and it's frequency is good, before selecting it in MAIN.
0h = No clock. Output will be tied low.
1h = Low frequency on-chip oscillator
2h = Low frequency crystal oscillator
3h = External LF clock through GPI.
1-0MAINR/W0hSelect the main low frequency clock source.
If running, this clock will be used to generate LFTICK and as CLKULL during STANDBY.
If not running, LFTICK will be generated from HFOSC and STANDBY entry will be prevented.
0h = No LF clock selected. LFTICK will be generated from HFOSC, STANDBY entry will be prevented.
1h = Low frequency on-chip oscillator
2h = Low frequency crystal oscillator
3h = External LF clock through GPI.

6.9.22 TDCCLKSEL Register (Offset = C4h) [Reset = 00000000h]

TDCCLKSEL is shown in Table 6-27.

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Internal. Only to be used through TI provided API.

Table 6-27 TDCCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0REFCLKR/W0hInternal. Only to be used through TI provided API.

6.9.23 ADCCLKSEL Register (Offset = C8h) [Reset = 00000000h]

ADCCLKSEL is shown in Table 6-28.

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ADC clock selection

Table 6-28 ADCCLKSEL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SRCR/W0hSelect ADC clock source
Change only while ADC is disabled.
0h = 48MHz CLKSVT
1h = 48MHz HFXT

6.9.24 LFCLKSTAT Register (Offset = E0h) [Reset = 00000000h]

LFCLKSTAT is shown in Table 6-29.

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Low-frequency clock status

Table 6-29 LFCLKSTAT Register Field Descriptions
BitFieldTypeResetDescription
31GOODR0hLow frequency clock good
Note: This is only a coarse frequency check based on LFQUALCTL. The clock may not be accurate enough for timing purposes.
30-26RESERVEDR0hReserved
25FLTSETTLEDR0hLFINC filter is running and settled.
24LFTICKSRCR0hSource of LFTICK.
0h = LFTICK generated from the selected LFCLK
1h = LFTICK generated from CLKULL (LFCLK not available)
23-22LFINCSRCR0hSource of LFINC used by the RTC.
This value depends on LFINCOVR.OVERRIDE, LF clock availability, HF tracking loop status and the device state (ACTIVE/STANDBY).
0h = Using measured value.
This value is updated by hardware and can be read from LFINC.
1h = Using filtered / average value.
This value is updated by hardware and can be read and updated in LFINCCTL.INT.
2h = Using override value from LFINCOVR.LFINC
3h = Using FAKE LFTICKs with corresponding LFINC value.
21-0LFINCR0hMeasured value of LFINC.
Given in microseconds with 16 fractional bits.
This value is calculated by Hardware.
It is the LFCLK period according to CLKULL cycles.

6.9.25 HFXTSTAT Register (Offset = E4h) [Reset = 00000000h]

HFXTSTAT is shown in Table 6-30.

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HFXT status information

Table 6-30 HFXTSTAT Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30-16STARTUPTIMER0hHFXT startup time
Can be used by software to plan starting HFXT ahead in time.
Measured whenever HFXT is enabled in CLKULL periods (24MHz), from HFXTCTL.EN until the clock is good for radio operation (amplitude compensation is settled).
15-2RESERVEDR0hReserved
1FAULTR0hHFXT clock fault
Indicates a lower than expected HFXT frequency.
HFXT will not recover from this fault, disabling and re-enabling HFXT is required.
0GOODR0hHFXT clock available.
The frequency is not necessarily good enough for radio operation.

6.9.26 AMPADCSTAT Register (Offset = E8h) [Reset = 00000000h]

AMPADCSTAT is shown in Table 6-31.

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Internal. Only to be used through TI provided API.

Table 6-31 AMPADCSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0hReserved
24COMPOUTR0hInternal. Only to be used through TI provided API.
23RESERVEDR0hReserved
22-16PEAKRAWR0hInternal. Only to be used through TI provided API.
15-8PEAKR0hInternal. Only to be used through TI provided API.
7RESERVEDR0hReserved
6-0BIASR0hInternal. Only to be used through TI provided API.

6.9.27 TRACKSTAT Register (Offset = ECh) [Reset = 00000000h]

TRACKSTAT is shown in Table 6-32.

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HFOSC tracking loop status information

Table 6-32 TRACKSTAT Register Field Descriptions
BitFieldTypeResetDescription
31LOOPERRVLDR0hCurrent HFOSC tracking error valid
This bit is one if the tracking loop is running and the error value is valid.
30RESERVEDR0hReserved
29-16LOOPERRR0hCurrent HFOSC tracking error
15-13RESERVEDR0hReserved
12-0FINETRIMR0hCurrent HFOSC Fine-trim value
This field uses the internal fractional representation (sign, 4 integer bits, 8 fractional bits).
The actual trim value applied to the oscillator is delta-sigma modulated 5 bits non-signed
(inverted sign bit + integer bits).

6.9.28 AMPSTAT Register (Offset = F0h) [Reset = 00000000h]

AMPSTAT is shown in Table 6-33.

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HFXT Amplitude Compensation Status

Table 6-33 AMPSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-25STATER0hCurrent AMPCOMP FSM state.
0h = FSM in idle state
1h = Starting LDO
2h = Second shutdown state
3h = Injecting HFOSC for fast startup
4h = Transition to HFXTTARG values
5h = Initial amplitude ramping with HFXTINIT values
6h = Amplitude down correction
7h = Post injection settle wait
Ah = First shutdown state
Ch = TCXO settled state
Eh = Amplitude up correction
Fh = Settled state
24-18IDACR0hCurrent IDAC control value.
17-14IREFR0hCurrent IREF control value.
13-8Q2CAPR0hCurrent Q2CAP control value.
7-2Q1CAPR0hCurrent Q1CAP control value.
1CTRLATTARGETR0hHFXT control values match target values.
This applies to IREF, Q1CAP, Q2CAP values.
0AMPGOODR0hHFXT amplitude good

6.9.29 ATBCTL0 Register (Offset = 100h) [Reset = 00000000h]

ATBCTL0 is shown in Table 6-34.

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Internal. Only to be used through TI provided API.

Table 6-34 ATBCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-0SELR/W0hInternal. Only to be used through TI provided API.

6.9.30 ATBCTL1 Register (Offset = 104h) [Reset = 00000000h]

ATBCTL1 is shown in Table 6-35.

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Internal. Only to be used through TI provided API.

Table 6-35 ATBCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0hReserved
14-13LFOSCR/W0hInternal. Only to be used through TI provided API.
12NABIASR/W0hInternal. Only to be used through TI provided API.
11RESERVEDR0hReserved
10LFXTR/W0hInternal. Only to be used through TI provided API.
9-8LFMONR/W0hInternal. Only to be used through TI provided API.
7HFXTR/W0hInternal. Only to be used through TI provided API.
6-1RESERVEDR0hReserved
0HFOSCR/W0hInternal. Only to be used through TI provided API.

6.9.31 DTBCTL Register (Offset = 108h) [Reset = 00000000h]

DTBCTL is shown in Table 6-36.

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Digital test bus mux control

Table 6-36 DTBCTL Register Field Descriptions
BitFieldTypeResetDescription
31-23RESERVEDR0hReserved
22-18DSEL2R/W0hInternal. Only to be used through TI provided API.
17-13DSEL1R/W0hInternal. Only to be used through TI provided API.
12-8DSEL0R/W0hInternal. Only to be used through TI provided API.
7-4CLKSELR/W0hSelect clock to output on DTB[0]
0h = Select CLKULL (24 MHz during ACTIVE, 32kHz during STANDBY)
1h = Select CLKSVT (48 MHz)
2h = Select CLKADC (48 MHz)
4h = Select tracking loop reference clock
7h = Select LFCLK (selected by LFCLKSEL.MAIN)
Ah = Select HFOSC after qualification
Ch = Select HFXT divided by 8
Dh = Select HFXT
Eh = Select LFOSC
Fh = Select LFXT
3-1RESERVEDR0hReserved
0ENR/W0hEnable DTB output

6.9.32 TRIM0 Register (Offset = 110h) [Reset = 00000000h]

TRIM0 is shown in Table 6-37.

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Internal. Only to be used through TI provided API.

Table 6-37 TRIM0 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8-5HFOSC_CAPR/W0hInternal. Only to be used through TI provided API.
4-0HFOSC_COARSER/W0hInternal. Only to be used through TI provided API.

6.9.33 TRIM1 Register (Offset = 114h) [Reset = 006F94D6h]

TRIM1 is shown in Table 6-38.

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Internal. Only to be used through TI provided API.

Table 6-38 TRIM1 Register Field Descriptions
BitFieldTypeResetDescription
31-30HFXTSLICERR/W0hInternal. Only to be used through TI provided API.
29-28PEAKIBIASR/W0hInternal. Only to be used through TI provided API.
27NABIAS_UDIGLDOR/W0hInternal. Only to be used through TI provided API.
26-24LDOBWR/W0hInternal. Only to be used through TI provided API.
23-20LDOFBR/W6hInternal. Only to be used through TI provided API.
19-16LFDLYR/WFhInternal. Only to be used through TI provided API.
15NABIAS_LFOSCR/W1hInternal. Only to be used through TI provided API.
14-8NABIAS_RESR/W14hInternal. Only to be used through TI provided API.
7-0LFOSC_CAPR/WD6hInternal. Only to be used through TI provided API.

6.9.34 HFXTINIT Register (Offset = 118h) [Reset = 147F8000h]

HFXTINIT is shown in Table 6-39.

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Initial values for HFXT ramping

Table 6-39 HFXTINIT Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-23AMPTHRR/W28hAmplitude threshold during HFXT ramping
22-16IDACR/W7FhInitial HFXT IDAC current
15-12IREFR/W8hInitial HFXT IREF current
11-6Q2CAPR/W0hInitial HFXT Q2 cap trim
5-0Q1CAPR/W0hInitial HFXT Q1 cap trim

6.9.35 HFXTTARG Register (Offset = 11Ch) [Reset = 54464B6Dh]

HFXTTARG is shown in Table 6-40.

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Target values for HFXT ramping

Table 6-40 HFXTTARG Register Field Descriptions
BitFieldTypeResetDescription
31-30AMPHYSTR/W1hADC hysteresis used during IDAC updates.
Every AMPCFG1.INTERVAL, IDAC will be regulated
- up as long as ADC < AMPTHR
- down as long as ADC > AMPTHR+AMPHYST
29-23AMPTHRR/W28hMinimum HFXT amplitude
22-16IDACR/W46hMinimum IDAC current
15-12IREFR/W4hTarget HFXT IREF current
11-6Q2CAPR/W2DhTarget HFXT Q2 cap trim
5-0Q1CAPR/W2DhTarget HFXT Q1 cap trim

6.9.36 HFXTDYN Register (Offset = 120h) [Reset = 14464B6Dh]

HFXTDYN is shown in Table 6-41.

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Alternative target values for HFXT configuration
Software can change these values to dynamically transition the HFXT configuration while HFXT is running.
Set SEL to select the alternative set of target values.

Table 6-41 HFXTDYN Register Field Descriptions
BitFieldTypeResetDescription
31SELR/W0hSelect the dynamic configuration.
Amplitude ramping will always happen using the values in HFXTINIT, and HFXTTARG.
Afterwards, this bit can be used to select between HFXTTARG and HFXTDYN.
Hardware will ensure a smooth transition of analog control signals.
0h = Select configuration in HFXTTARG.
1h = Select configuration in HFXTDYN.
30RESERVEDR0hReserved
29-23AMPTHRR/W28hMinimum HFXT amplitude
22-16IDACR/W46hMinimum IDAC current
15-12IREFR/W4hTarget HFXT IREF current
11-6Q2CAPR/W2DhTarget HFXT Q2 cap trim
5-0Q1CAPR/W2DhTarget HFXT Q1 cap trim

6.9.37 AMPCFG0 Register (Offset = 124h) [Reset = 00348882h]

AMPCFG0 is shown in Table 6-42.

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Amplitude Compensation Configuration 0

Table 6-42 AMPCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-28Q2DLYR/W0hQ2CAP change delay.
Number of clock cycles to wait before changing Q2CAP by one step.
Clock frequency defined in FSMRATE.
27-24Q1DLYR/W0hQ1CAP change delay.
Number of clock cycles to wait before changing Q1CAP by one step.
Clock frequency defined in FSMRATE.
23-20ADCDLYR/W3hADC and PEAKDET startup time.
Number of clock cycles to wait after enabling the PEAKDET and ADC before the first measurement.
Clock frequency defined in FSMRATE.
19-15LDOSTARTR/W9hLDO startup time.
Number of clock cycles to bypass the LDO resistors for faster startup.
Clock frequency defined in FSMRATE.
14-10INJWAITR/W2hInject HFOSC for faster HFXT startup.
This value specifies the number of clock cycles to wait after injection is done.
The clock speed is defined in FSMRATE.
9-5INJTIMER/W4hInject HFOSC for faster HFXT startup.
This value specifies the number of clock cycles the injection is enabled.
The clock speed is defined in FSMRATE.
Set to 0 to disable injection.
4-0FSMRATER/W2hUpdate rate for the AMPCOMP update rate.
Also affects the clock rate for the Amplitude ADC.
The update rate is 6MHz / (FSMRATE+1).
0h = 6 MHz
1h = 3 MHz
2h = 2 MHz
5h = 1 MHz
Bh = 500 kHz
17h = 250 kHz

6.9.38 AMPCFG1 Register (Offset = 128h) [Reset = 260FF0FFh]

AMPCFG1 is shown in Table 6-43.

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Amplitude Compensation Configuration 1

Table 6-43 AMPCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-28IDACDLYR/W2hIDAC change delay.
Time to wait before changing IDAC by one step.
This time needs to be long enough for the crystal to settle.
The number of clock cycles to wait is IDACDLY<<4 + 15.
Clock frequency defined in AMPCFG0.FSMRATE.
27-24IREFDLYR/W6hIREF change delay.
Number of clock cycles to wait before changing IREF by one step.
Clock frequency defined in AMPCFG0.FSMRATE.
23-12BIASLTR/WFFhLifetime of the amplitude ADC bias value.
This value specifies the number of adjustment intervals,
until the ADC bias value has to be measured again.
Set to 0 to disable automatic bias measurements.
11-0INTERVALR/WFFhInterval for amplitude adjustments.
Set to 0 to disable periodic adjustments.
This value specifies the number of clock cycles between adjustments.
The clock speed is defined in AMPCFG0.FSMRATE.

6.9.39 LOOPCFG Register (Offset = 12Ch) [Reset = 605E33B3h]

LOOPCFG is shown in Table 6-44.

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Configuration Register for the Tracking Loop

Table 6-44 LOOPCFG Register Field Descriptions
BitFieldTypeResetDescription
31-26FINETRIM_INITR/W18hInitial value for the resistor fine trim
25-21BOOST_TARGETR/W2hNumber of error-updates using BOOST values, before using KI/KP
20-18KP_BOOSTR/W7hProportional loop coefficient during BOOST
17-15KI_BOOSTR/W4hIntegral loop coefficient during BOOST
14-10SETTLED_TARGETR/WChNumber of updates before HFOSC is considered "settled"
9-6OOR_LIMITR/WEhOut-of-range threshold
5-3KPR/W6hProportional loop coefficient
2-0KIR/W3hIntegral loop coefficient

6.9.40 TDCCTL Register (Offset = 200h) [Reset = 00000000h]

TDCCTL is shown in Table 6-45.

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Internal. Only to be used through TI provided API.

Table 6-45 TDCCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0CMDW0hInternal. Only to be used through TI provided API.

6.9.41 TDCSTAT Register (Offset = 204h) [Reset = 00000006h]

TDCSTAT is shown in Table 6-46.

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Internal. Only to be used through TI provided API.

Table 6-46 TDCSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9STOP_BFR0hInternal. Only to be used through TI provided API.
8START_BFR0hInternal. Only to be used through TI provided API.
7SATR0hInternal. Only to be used through TI provided API.
6DONER0hInternal. Only to be used through TI provided API.
5-0STATER6hInternal. Only to be used through TI provided API.

6.9.42 TDCRESULT Register (Offset = 208h) [Reset = 00000002h]

TDCRESULT is shown in Table 6-47.

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Internal. Only to be used through TI provided API.

Table 6-47 TDCRESULT Register Field Descriptions
BitFieldTypeResetDescription
31-0VALUER2hInternal. Only to be used through TI provided API.

6.9.43 TDCSATCFG Register (Offset = 20Ch) [Reset = 00000000h]

TDCSATCFG is shown in Table 6-48.

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Internal. Only to be used through TI provided API.

Table 6-48 TDCSATCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-0LIMITR/W0hInternal. Only to be used through TI provided API.

6.9.44 TDCTRIGSRC Register (Offset = 210h) [Reset = 00000000h]

TDCTRIGSRC is shown in Table 6-49.

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Internal. Only to be used through TI provided API.

Table 6-49 TDCTRIGSRC Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15STOP_POLR/W0hInternal. Only to be used through TI provided API.
14-13RESERVEDR0hReserved
12-8STOP_SRCR/W0hInternal. Only to be used through TI provided API.
7START_POLR/W0hInternal. Only to be used through TI provided API.
6-5RESERVEDR0hReserved
4-0START_SRCR/W0hInternal. Only to be used through TI provided API.

6.9.45 TDCTRIGCNT Register (Offset = 214h) [Reset = 00000000h]

TDCTRIGCNT is shown in Table 6-50.

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Internal. Only to be used through TI provided API.

Table 6-50 TDCTRIGCNT Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CNTR/W0hInternal. Only to be used through TI provided API.

6.9.46 TDCTRIGCNTLOAD Register (Offset = 218h) [Reset = 00000000h]

TDCTRIGCNTLOAD is shown in Table 6-51.

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Internal. Only to be used through TI provided API.

Table 6-51 TDCTRIGCNTLOAD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0CNTR/W0hInternal. Only to be used through TI provided API.

6.9.47 TDCTRIGCNTCFG Register (Offset = 21Ch) [Reset = 00000000h]

TDCTRIGCNTCFG is shown in Table 6-52.

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Internal. Only to be used through TI provided API.

Table 6-52 TDCTRIGCNTCFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ENR/W0hInternal. Only to be used through TI provided API.

6.9.48 TDCPRECTL Register (Offset = 220h) [Reset = 00000000h]

TDCPRECTL is shown in Table 6-53.

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Internal. Only to be used through TI provided API.

Table 6-53 TDCPRECTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7RESET_NR/W0hInternal. Only to be used through TI provided API.
6RATIOR/W0hInternal. Only to be used through TI provided API.
5RESERVEDR0hReserved
4-0SRCR/W0hInternal. Only to be used through TI provided API.

6.9.49 TDCPRECNTR Register (Offset = 224h) [Reset = 00000000h]

TDCPRECNTR is shown in Table 6-54.

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Internal. Only to be used through TI provided API.

Table 6-54 TDCPRECNTR Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0hReserved
16CAPTW0hInternal. Only to be used through TI provided API.
15-0CNTR0hInternal. Only to be used through TI provided API.

6.9.50 WDTCNT Register (Offset = 300h) [Reset = 00000000h]

WDTCNT is shown in Table 6-55.

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WDT counter value register

Table 6-55 WDTCNT Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hCounter value.
A write to this field immediately starts (or restarts) the counter. It will count down from the written value.
If the counter reaches 0, a reset will be generated.
A write value of 0 immediately generates a reset.
This field is only writable if not locked. See WDTLOCK register.
Writing this field will automatically activate the lock.
A read returns the current value of the counter.

6.9.51 WDTTEST Register (Offset = 304h) [Reset = 00000000h]

WDTTEST is shown in Table 6-56.

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WDT test mode register

Table 6-56 WDTTEST Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STALLENR/W0hWDT stall enable
This field is only writable if not locked. See WDTLOCK register.
0h = DISABLE
WDT continues counting while the CPU is stopped by a debugger.
1h = ENABLE
WDT stops counting while the CPU is stopped by a debugger.

6.9.52 WDTLOCK Register (Offset = 308h) [Reset = 00000001h]

WDTLOCK is shown in Table 6-57.

Return to the Summary Table.

WDT lock register

Table 6-57 WDTLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-0STATR/W1hA write with value 0x1ACCE551 unlocks the watchdog registers for write access.
A write with any other value locks the watchdog registers for write access.
Writing the WDTCNT register will also lock the watchdog registers.
A read of this field returns the state of the lock (0=unlocked, 1=locked).