ZHCSJM7 April 2019 BQ79606A-Q1
PRODUCTION DATA.
SPI_CFG Register Address: 0x154 | |||||||
B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 |
RSVD | CPOL | CPHA | SS_STAT | SPI_EN | NUMBITS[2] | NUMBITS[1] | NUMBITS[0] |
0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
R | RW | RW | RW | RW | RW | RW | RW |
RSVD | Reserved | ||||||
CPOL | Sets the SCLK polarity
0: Idles low and clocks high 1: Idles high and clocks low |
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CPHA | Sets the edge of SCLK where data is sampled on MISO
0: First clock transition 1: Second clock transition |
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SS_STAT | Programs the state of SS
0: Output low 1: Output high |
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SPI_EN | Enables the SPI master function. The SPI master function has priority over normal GPIO function for GPIOs 3-6. Any configuration bits for these GPIOs is ignored.
0: Disabled 1: Enabled |
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NUMBITS[2:0] | SPI Transaction length. Set number of SPI bits to read/write
000: 8 bits 001:111 Corresponds to 1 to 7 bits |