SPRUJ62 December   2022 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

3.5 Power Monitoring

The EVM includes power monitoring/measurement of 32 discrete power rails. The on-board analog-to-digital converters (INA226) are accessed via I2C. The processor can access using I2C1. The test automation [J50] can access the I2C bus, or it can be access externally via 5-pin header [J30]. Due to the number of rails, the ADCs are split across two I2C buses. Selection of the buses is done via mux setting (see Section 3.4)

Table 3-5 GPIO Mapping for Expansion IO
Bus #1 Address Power Rail Nom V Shunt Value Bus #2 Address Power Rail Nom V Shunt Value
0x40

Processor MCU VDD

(VDD_MCU_0V85)

 0.85V 10m-ohm 0x40 Processor IO at 1.8V (VDD_IO_1V8) 1.8V 10m-ohm
0x41

Processor MCU RAM

(VDD_MCU_RAM_0V85)

 0.85V 10m-ohm 0x41 Processor IO at 3.3V (VDD_IO_3V3) 3.3V 10m-ohm
0x42 (VDA_MCU_1V8) 1.8V 10m-ohm 0x42 Processor Dual Voltage IO (VDD_SD_DV) DV 10m-ohm
0x43

Processor MCU IO at 3.3V

(VDD_MCUIO_3V3)

 3.3V 10m-ohm 0x43

LPDDR4 Memory (VDD1)

(VDD1_DDR_1V8)

 1.8V 10m-ohm
0x44

Processor MCU IO at 1.8V

(VDD_MCUIO_1V8)

 1.8V 10m-ohm 0x44 (VDD_DDR_SOC_1V1) 1.1V
0x45 (VDD_CORE_0V8) N/A N/A 0x45 (VCCA_3V3_CORE) 3.3V 5m-ohm
0x46 (VDD_RAM_0V85) 0.85V 10m-ohm 0x46

MCU Peripherals at 1.8V

(VSYS_MCUIO_1V8)

 1.8V 10m-ohm
0x47 (VDD_GPIORET_WK_0V8) 0.8V 10m-ohm 0x47

MCU Peripherals at 3.3V

(VSYS_MCUIO_3V3)

 3.3V 10m-ohm
0x48 (VDD_CPU_AVS) N/A N/A 0x48 (VSYS_IO_1V8) 1.8V 10m-ohm
0x49 (VSYS_GPIORET_IO_3V3) 3.3V 10m-ohm 0x49 (VSYS_IO_3V3) 3.3V 10m-ohm
0x4A

Processor LPDDR IO

(VDD_DDR_1V1)

 N/A N/A 0x4A (VCC_12V0_N) 12V ??m-Ohm
0x4B (VDD_PHYCORE_0V8) 0.8V 10m-ohm 0x4B (VSYS_5V0) 5V0
0x4C (VDA_PLL_1V8) 1.8V 10m-ohm 0x4C (VSYS_3V3) 3V3
0x4D (VDA_PHY_1V8) 1.8V 10m-ohm 0x4D (VCCA_3V3_DDR) 3.3V 10m-ohm
0x4E (VDA_USB_3V3) 3.3V 10m-ohm 0x4E (VDA_DLL_0V8) 0.8V 10m-ohm
0x4F (VDD_GPIORET_IO_3V3) 3.3V 10m-ohm 0x4F (VCCA_3V3_CPU_AVS) 3.3V 5m-ohm
Note: In the table, the ‘(_name)’ refers to the net name used in the schematic.