SPRUJ62 December   2022 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

3.8 Identification EEPROM

The EVM board identity and revision information are stored in an on-board EEPROM. The first 259 bytes of the memory are pre-programmed with EVM identification information. The format of the data is provided in Table 3-6. The remaining bytes are available to user defined storage.

Table 3-6 Board ID Information
Field Name Offset /Size Value Comments
MAGIC 0000 / 4B (Hex) 0xEE3355AA Header Identifier
M_TYPE 0004 / 1B (Hex) 0x1 Fixed length and variable position board ID header
M_LENGTH 0005 / 2B (Hex) 0x10B Size of payload
B_TYPE 0007 / 1B (Hex) 0x10 Payload type
B_LENGTH 0008 / 2B (Hex) 0x2E Offset to next header
B_NAME 000A / 16B (CHAR) J784S4X-EVM Name of the board
DESGIN_REV 001A / 2B (CHAR) E1 Revision number of the design
PROC_NBR 001C / 4B (CHAR) 141 PROC number
VARIANT 0020 / 2B (CHAR) 1 Design variant number
PCB_REV 0022 / 2B (CHAR) E1 Revision number of the PCB
SCHBOM_REV 0024 / 2B (CHAR) 0 Revision number of the schematic
SWR_REV 0026 / 2B (CHAR) 1 first software release number
VENDORID 0028 / 2B (CHAR) 1 0x1: Manufactured by Mistral
BUILD_WK 002A / 2B (CHAR) week of the year of production
BUILD_YR 002C / 2B (CHAR) year of production
BOARDID 002E / 6B (CHAR) 0
SERIAL_NBR 0034 / 4B (CHAR) 4 incrementing board number
DDR_TYPE 0038 / 1B (Hex) 0x11 DDR Header Identifier
DDR_LENGTH 0039 / 2B (Hex) 0x2 offset to next header
DDR_CONTROL 003B / 2B (Hex) 0xC560

DDR Control Word

Bit 1:0 = ‘00’ First DDR

Bit 3:2 = ‘00’ No SPD

Bit 5:4 = ‘10’ LPDDR4

Bit 7:6 = ‘01’ 32 bits

Bit 9:8 = ‘01’ 32 bits

Bit 10 = ‘1’ dual rank

Bit 13:11 = ‘000’ Density 64 Gb(bit 0 to 3)

Bit 14 = ‘1’ ECC bits present (inline, not separate bits)

Bit 15 = ‘1’ Density 64 Gb (bit 4)
DDR_TYPE 003D / 1B (Hex) 0x11 DDR Header Identifier
DDR_LENGTH 003E / 2B (Hex) 0x2 offset to next header
DDR_CONTROL 0040 / 2B (Hex) 0xC560 DDR Control Word)
DDR_TYPE 0042 / 1B (Hex) 0x11 DDR Header Identifier
DDR_LENGTH 0043 / 2B (Hex) 0x2 offset to next header
DDR_CONTROL 0045 / 2B (Hex) 0xC560 DDR Control Word)
DDR_TYPE 0047 / 1B (Hex) 0x11 DDR Header Identifier
DDR_LENGTH 0048 / 2B (Hex) 0x2 offset to next header
DDR_CONTROL 004A / 2B (Hex) 0xC560 DDR Control Word)
MAC_TYPE 004C / 1B (Hex) 0x13 MAC address Header Identifier
MAC_LENGTH 004D / 2B (Hex) 0xC2 Size of payload
MAC_CONTROL 004F / 1B (Hex) 0x0 MAC header control word (0 = 1 MAC address)
MAC_ADDRS 0051 / 192B (Hex) MAC address
END_LIST 0111 / 1B (Hex) 0xFE End Marker