SPRUJ62 December   2022 TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features and Interfaces
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Input
      1. 2.1.1 Power Input [J7] [J3] with LED for Status [LD4][LD5]
      2. 2.1.2 Power Control [SW1] with LED for Status [LD7][LD8][LD9]
      3. 2.1.3 Power Budget Considerations
    2. 2.2 User Inputs
      1. 2.2.1 Board Configuration Settings [SW2] [SW4] [SW13] [SW16]
      2. 2.2.2 Boot Configuration Settings [SW7] [ SW11]
      3. 2.2.3 Reset Pushbuttons [SW9] [ SW10] [SW12] [SW14]
      4. 2.2.4 User Pushbuttons [SW3] [SW5] [SW6] [SW8] [SW15] with User LED Indication [LD2] [LD3]
    3. 2.3 Standard Interfaces
      1. 2.3.1 Uart-Over-USB [J48] [J49] with LED for Status [LD11] [LD12]
      2. 2.3.2 Gigabit Ethernet [J39] [J40] with Integrated LEDs for Status
      3. 2.3.3 USB3.1 Gen1 Interface [J4]
      4. 2.3.4 USB2.0 Interface [J5]
      5. 2.3.5 PCIe Card Slot [J14] [J17]
      6. 2.3.6 Display Port Interfaces [J8] [J9]
      7. 2.3.7 MicroSD Card Cage [J53]
      8. 2.3.8 Stereo Audio Interface [J29]
      9. 2.3.9 JTAG/Emulation Interface [J23] [J1]
    4. 2.4 Expansion Interfaces
      1. 2.4.1  Heatsink [ACC1] with Fan Header [J24]
      2. 2.4.2  CAN-FD Connectors [J41-J46]
      3. 2.4.3  LIN Connectors [J28]
      4. 2.4.4  Serial Ethernet Expansion Interfaces [J52] [J51]
      5. 2.4.5  Camera Interfaces [J55] [J57]
      6. 2.4.6  Automation and Control Connector [J50]
      7. 2.4.7  ADC [J27]
      8. 2.4.8  SPI [J26]
      9. 2.4.9  CSI-TX [J10]
      10. 2.4.10 Accessory Power Connector [J47]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
    5. 3.5 Power Monitoring
    6. 3.6 Shared Interfaces / Signal Muxing
    7. 3.7 Power Delivery Network (PDN)
    8. 3.8 Identification EEPROM

3.2 Interface Mapping

The EVM interface mapping tables is provided in Table 3-1.

Table 3-1 Interface Mapping Table
Connected Peripheral Processor Resource(s) Component/Part Numbers
Memory, LPDDR4 DRAM DDR0, DDR1, DDR2, DDR3 (4x) Micron, MT53E2G32D4DE-046 AUT:C
Memory, xSPI NOR Flash MCU_OSPI0 Cypress, S28HS512TGABHM010
Memory, Octal NAND MCU_OSPI0 Winbond, W35N01JWTBAG
Memory, Quad SPI NOR Flash MCU_OSPI1 Micron, MT25QU512ABB8E12-0SIT
Memory, eMMC MMC0 Micron, MTFC16GAPALBH-AAT ES
Memory, microSD Card MMC1
EEPROM, Board Identification WKUP_I2C0 On-Semi, CAT24C256WI-GT3
EEPROM, Boot MCU_I2C0 Microchip Tech, AT24CM01
Memory, UFS 2L Gear3 UFS0 Toshiba, THGAF8G8T23BAIL
Wired Ethernet MCU_RGMII1, RGMII1 (2x) Texas Instruments, DP83867ERGZT
USB Type C + CC Controller USB0 + SERDES0 (L2, L3) Texas Instruments, TUSB321RWBR
USB Type A (2x) USB0 Texas Instruments, TUSB4041IPAP
Audio Codec McASP0 Texas Instruments, PCM3168APAP
PCIe 4L Card Slot PCIe1 / SERDES0 (L0, L1)
PCIe 4L Card Slot PCIe0, SERDES1
Quad USART Terminal UART 8,5,2 & 3 FTDI, FT4232HL
Dual USART Terminal WKUP_UART0, MCU_UART0 FTDI, FT2232HL
CAN (6x) MCU_MCAN0, MCU_MCAN1, MCAN4, MCAN5, MCAN16 Texas Instruments, TCAN1042HGVD
MCAN3 Texas Instruments, TCAN1043-Q1
LIN (2x) UART6, UART9 Texas Instruments, TLIN1022DMTTQ1
CSI RX Interface CSI0, CSI1, CSI2 QSH Connector-J57(QSH-020-01-L-D-DP-A-K)
Display Port DP0
DSI0 Texas Instruments, SN65DSI86IPAPQ1
ADC Header MCU_ADC0
Note: MCU_OSPI1 is connected to two different flash memories, target memory selected via a mux.