ZHCSR89A December   2022  – August 2023 ADS131B23

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagram
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Offset Drift Measurement
    2. 7.2 Gain Drift Measurement
    3. 7.3 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Naming Conventions
      2. 8.3.2 Precision Voltage References (REFA, REFB)
      3. 8.3.3 Clocking (MCLK, OSCM, OSCD)
      4. 8.3.4 ADC1y
        1. 8.3.4.1 ADC1y Input Multiplexer
        2. 8.3.4.2 ADC1y Programmable Gain Amplifier (PGA)
        3. 8.3.4.3 ADC1y ΔΣ Modulator
        4. 8.3.4.4 ADC1y Digital Filter
        5. 8.3.4.5 ADC1y Offset and Gain Calibration
        6. 8.3.4.6 ADC1y Conversion Data
      5. 8.3.5 ADC2y
        1. 8.3.5.1 ADC2y Input Multiplexer
        2. 8.3.5.2 ADC2y Programmable Gain Amplifier (PGA)
        3. 8.3.5.3 ADC2y ΔΣ Modulator
        4. 8.3.5.4 ADC2y Digital Filter
        5. 8.3.5.5 ADC2y Offset and Gain Calibration
        6. 8.3.5.6 ADC2y Sequencer
        7. 8.3.5.7 VCMy Buffers
        8. 8.3.5.8 ADC2y Measurement Configurations
        9. 8.3.5.9 ADC2y Conversion Data
      6. 8.3.6 General-Purpose Digital Inputs and Outputs (GPIO0 to GPIO4)
        1. 8.3.6.1 GPIOx PWM Output Configuration
        2. 8.3.6.2 GPIOx PWM Input Readback
      7. 8.3.7 General-Purpose Digital Inputs and Outputs (GPIO0A, GPIO1A, GPIO0B, GPIO1B)
      8. 8.3.8 Monitors and Diagnostics
        1. 8.3.8.1  Supply Monitors
        2. 8.3.8.2  Clock Monitors
        3. 8.3.8.3  Digital Monitors
          1. 8.3.8.3.1 Register Map CRC
          2. 8.3.8.3.2 Memory Map CRC
          3. 8.3.8.3.3 GPIO Readback
        4. 8.3.8.4  Communication Monitors
        5. 8.3.8.5  Fault Flags and Fault Masking
        6. 8.3.8.6  FAULT Pin
        7. 8.3.8.7  Diagnostics and Diagnostic Procedure
        8. 8.3.8.8  Indicators
        9. 8.3.8.9  Conversion and Sequence Counters
        10. 8.3.8.10 Supply Voltage Readback
        11. 8.3.8.11 Temperature Sensor (TSA)
        12. 8.3.8.12 Test DACs (TDACA, TDACB)
        13. 8.3.8.13 Open-Wire Detection
        14. 8.3.8.14 Missing Host Detection and MHD Pin
        15. 8.3.8.15 Overcurrent Comparators (OCCA, OCCB)
          1. 8.3.8.15.1 OCCA and OCCB Pins
          2. 8.3.8.15.2 Overcurrent Indication Response Time
    4. 8.4 器件功能模式
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset (POR)
        2. 8.4.1.2 RESETn Pin
        3. 8.4.1.3 RESET Command
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Active Mode
        2. 8.4.2.2 Standby Mode
        3. 8.4.2.3 Power-Down Mode
      3. 8.4.3 ADC Conversion Modes
        1. 8.4.3.1 ADC1y Conversion Modes
          1. 8.4.3.1.1 Continuous-Conversion Mode
          2. 8.4.3.1.2 Single-Shot Conversion Mode
          3. 8.4.3.1.3 Global-Chop Mode
            1. 8.4.3.1.3.1 Overcurrent Indication Response Time in Global-Chop Mode
        2. 8.4.3.2 ADC2y Sequencer Operation and Sequence Modes
          1. 8.4.3.2.1 Continuous Sequence Mode
          2. 8.4.3.2.2 Single-Shot Sequence Mode
          3. 8.4.3.2.3 Synchronized Single-Shot Sequence Mode Based on ADC1y Conversion Starts
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Serial Interface Signals
          1. 8.5.1.1.1 Chip Select (CSn)
          2. 8.5.1.1.2 Serial Data Clock (SCLK)
          3. 8.5.1.1.3 Serial Data Input (SDI)
          4. 8.5.1.1.4 Serial Data Output (SDO)
          5. 8.5.1.1.5 Data Ready (DRDYn)
        2. 8.5.1.2 Serial Interface Communication Structure
          1. 8.5.1.2.1 SPI Communication Frames
          2. 8.5.1.2.2 SPI Communication Words
          3. 8.5.1.2.3 STATUS Word
          4. 8.5.1.2.4 Communication Cyclic Redundancy Check (CRC)
          5. 8.5.1.2.5 Commands
            1. 8.5.1.2.5.1 NULL (0000 0000 0000 0000b)
            2. 8.5.1.2.5.2 RESET (0000 0000 0001 0001b)
            3. 8.5.1.2.5.3 LOCK (0000 0101 0101 0101b)
            4. 8.5.1.2.5.4 UNLOCK (0000 0110 0101 0101b)
            5. 8.5.1.2.5.5 WREG (011a aaaa aaa0 0nnnb)
            6. 8.5.1.2.5.6 RREG (101a aaaa aaan nnnnb)
          6. 8.5.1.2.6 SCLK Counter
          7. 8.5.1.2.7 SPI Timeout
          8. 8.5.1.2.8 Reading ADC1A, ADC1B, and ADC2A Conversion Data
          9. 8.5.1.2.9 DRDYn Pin Behavior
    6. 8.6 Register Map
      1. 8.6.1 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Minimum Interface Connections
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Current-Shunt Measurement
        2. 9.2.2.2 Battery-Pack Voltage Measurement
        3. 9.2.2.3 Shunt Temperature Measurement
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Options
        1. 9.3.1.1 Single Unregulated External 4-V to 16-V Supply (3.3-V Digital I/O Levels)
        2. 9.3.1.2 Single Regulated External 3.3-V Supply (3.3-V Digital IO Levels)
        3. 9.3.1.3 Single Regulated External 5-V Supply (5-V Digital I/O Levels)
      2. 9.3.2 Power-Supply Sequencing
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10器件和文档支持
    1. 10.1 文档支持
      1. 10.1.1 相关文档
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息
8.5.1.2.9 DRDYn Pin Behavior

This section provides details about the DRDYn pin behavior in various scenarios.

DRDYn transitions low whenever new conversion data complete on ADC1A or ADC1B, depending on which ADC drives the DRDYn signal as configured in the DRDY_CTRL bit. If DRDYn is low when a new conversion completes on ADC1y, then DRDYn drives high tw(DRH) before the DRDYn falling edge (see Figure 8-40 and Figure 8-42).

DRDYn transitions high after the conversion data for ADC1B are retrieved on SDO (Figure 8-39). If CSn is driven high before the ADC1B conversion data are retrieved, then DRDYn stays low, indicating that not all conversion data were read (Figure 8-40 and Figure 8-41).

Figure 8-41 shows that the same conversion data can be read multiple times until new conversions complete. The ADC1y conversion counters indicate if the same data were read again or if new data were read.

The device avoids data corruption if new conversions n+1 complete while conversion data n are being read. Conversion data n+1 are held in an internal buffer until the read of conversion data n is complete. In the following frame, conversion data n+1 are loaded into the SDO output buffer. DRDYn does not transition high after conversion data n have been read in this case to indicate that new conversion data n+1 are available for readout (see Figure 8-42).

Figure 8-43 illustrates that conversion data n+1 are lost when the host does not read the data before conversions n+2 complete. The ADC1y conversion counters are helpful in this situation to detect if the host missed reading the intermediate conversion results.

GUID-20220910-SS0I-P8SJ-JPQF-GL4LHTSCX4HH-low.svg Figure 8-39 DRDYn Pin Behavior: Reading All Conversion Data Before New Conversions Complete
GUID-20220910-SS0I-HS3S-JZRV-6XJQBRHGVCPB-low.svg Figure 8-40 DRDYn Pin Behavior: Incomplete Read of Conversion Data Before New Conversions Complete
GUID-20220910-SS0I-RWL7-JZ3S-QWWQ6CT7KQJK-low.svg Figure 8-41 DRDYn Pin Behavior: Incomplete Read of Conversion Data Followed by Complete Read of Same Conversion Data
GUID-20220910-SS0I-DFZ6-N8C3-NT4BTJNNKJ6Z-low.svg Figure 8-42 DRDYn Pin Behavior: Reading Conversion Data While New Conversions Complete
GUID-20220910-SS0I-H2RK-KCXK-QJSCND6XVLGG-low.svg Figure 8-43 DRDYn Pin Behavior: Missed Reading Intermediate Conversion Results

Setting the STARTy bit drives the DRDYn pin high at the last SCLK falling edge of the register data CRC word within the SPI frame where the CONVERSION_CTRL register is written. However, the old conversion data can still be read until the new conversions become available. Figure 8-44 shows the device behavior when setting the STARTy bit to abort an ongoing conversion and to restart new conversions while reading out conversion data. Figure 8-45 shows a scenario where new conversions complete while setting the STARTy bit and reading out conversion data.

GUID-20220910-SS0I-6LZQ-BRMT-KRTKQ7BV6BQG-low.svg Figure 8-44 DRDYn Pin Behavior: Setting the STARTy Bit While Reading Conversion Data
GUID-20220910-SS0I-GCFC-QH1J-MWXTQS93N63V-low.svg Figure 8-45 DRDYn Pin Behavior: Setting the STARTy Bit and Reading Conversion Data While New Conversions Complete