The ADS131B23 provides a set of indicator bits inside the STATUS_MSB and STATUS_LSB registers that help to verify the state of the device:

• Command response: The COMMAND_RESPONSE[3:0] bit field is transmitted in every SPI frame and provides feedback about the command that was received by the device in the previous frame. Information about which command was executed is also provided. See the COMMAND_RESPONSE[3:0] register bit field description for details.
• Lock state: The LOCK bit indicates if the device is currently locked or unlocked. See the Commands section for details on how to lock and unlock the device.
• Clock source: The CLOCK bit indicates which clock source the device is using as the main clock, either the internal main oscillator (OSCM) or an external clock provided at the CLK pin.
• Operating mode: The MODE bit indicates which mode the device is currently operating in, either active, standby, or power-down mode.
• ADC2A sequence active: The SEQ2A_ACTIVE bit indicates if a sequence on ADC2A is currently in progress.

An additional OTP_BANK status bit is provided in the DIGITAL_STATUS register. The device includes two one-time programmable (OTP) memory banks, bank 0 and bank 1. Device configuration and calibration data are stored during device production in those OTP banks. A corrupted OTP bank can cause undetermined device behavior or degraded device performance. The information in bank 0 is duplicated in bank 1 for redundancy. At device power-up or during reset, the device loads the content of OTP bank 0 into the internal memory. If the device fails to acquire the data from bank 0, then the device loads the content from OTP bank 1. The OTP_BANK bit indicates which bank was acquired. The device performs normally even when running from OTP bank 1.

If the device fails to acquire data from OTP bank 1 as well, then the memory map CRC fault flag is set to 0b. If resetting the device does not clear the MEM_MAP_CRC_FAULTn fault flag, consider the device damaged.