ZHCSPK7F November 2004 – January 2022 TPS2384
PRODUCTION DATA
After the chip address cycle, the TPS2384 accepts eight bits of port and register select data as defined in Table 8-2. The SCL line high-to-low transition after the eighth data bit then latches the selection of the appropriate internal register for the follow-on data read or write operation. After latching the eight-bit data field, the TPS2384 pulls the SDA_O line low for one clock cycle, for the acknowledge pulse.