ZHCSS38
july 2020
TSB82AF15-EP
PRODUCTION DATA
1
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
PCIe Differential Transmitter Output Ranges
6.6
PCIe Differential Receiver Input Ranges
6.7
PCIe Differential Reference Clock Input Ranges
6.8
Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)
6.9
Switching Characteristics
7
Operating Life Deration
8
Typical Characteristics
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Power-Up/Power-Down Sequencing
10.3.1.1
Power-Up Sequence
10.3.1.2
Power-Down Sequence
10.3.2
TSB82AF15-EP Reset Features
10.3.3
PCI Express (PCIe) Interface
10.3.3.1
External Reference Clock
10.3.3.2
Beacon and Wake
10.3.3.3
Initial Flow Control Credits
10.3.3.4
PCIe Message Transactions
10.3.4
PCI Interrupt Conversion to PCIe Messages
10.3.5
Two-Wire Serial-Bus Interface
10.3.5.1
Serial-Bus Interface Implementation
10.3.5.2
Serial-Bus Interface Protocol
10.3.5.3
Serial-Bus EEPROM Application
10.3.5.4
Accessing Serial-Bus Devices Through Software
10.3.6
General-Purpose I/O (GPIO) Interface
10.4
Device Functional Modes
10.4.1
Advanced Error Reporting Registers
10.4.2
Data Error Forwarding Capability
10.4.3
Set Slot Power Limit Functionality
10.4.4
PCIe and PCI Bus Power Management
10.5
Programming
10.5.1
1394b OHCI Controller Functionality
10.5.1.1
1394b OHCI Power Management
10.5.1.2
1394b OHCI and V AUX
10.5.1.3
1394b OHCI and Reset Options
10.5.1.4
1394b OHCI PCI Bus Master
10.5.1.5
1394b OHCI Subsystem Identification
10.5.1.6
1394b OHCI PME Support
10.6
Register Maps
10.6.1
Classic PCI Configuration Space
10.6.1.1
Vendor ID Register
10.6.1.2
Device ID Register
10.6.1.3
Command Register
10.6.1.4
Status Register
10.6.1.5
Class Code and Revision ID Register
10.6.1.6
Cache Line Size Register
10.6.1.7
Primary Latency Timer Register
10.6.1.8
Header Type Register
10.6.1.9
BIST Register
10.6.1.10
Device Control Base Address Register
10.6.1.11
Scratchpad RAM Base Address
10.6.1.12
Primary Bus Number Register
10.6.1.13
Secondary Bus Number Register
10.6.1.14
Subordinate Bus Number Register
10.6.1.15
Secondary Latency Timer Register
10.6.1.16
I/O Base Register
10.6.1.17
I/O Limit Register
10.6.1.18
Secondary Status Register
10.6.1.19
Memory Base Register
10.6.1.20
Memory Limit Register
10.6.1.21
Prefetchable Memory Base Register
10.6.1.22
Prefetchable Memory Limit Register
10.6.1.23
Prefetchable Base Upper 32 Bits Register
10.6.1.24
Prefetchable Limit Upper 32 Bits Register
10.6.1.25
I/O Base Upper 16 Bits Register
10.6.1.26
I/O Limit Upper 16 Bits Register
10.6.1.27
Capabilities Pointer Register
10.6.1.28
Interrupt Line Register
10.6.1.29
Interrupt Pin Register
10.6.1.30
Bridge Control Register
10.6.1.31
PM Capability ID Register
10.6.1.32
Next Item Pointer Register
10.6.1.33
Power Management Capabilities Register
10.6.1.34
Power Management Control/Status Register
10.6.1.35
Power Management Bridge Support Extension Register
10.6.1.36
Power Management Data Register
10.6.1.37
MSI Capability ID Register
10.6.1.38
Next Item Pointer Register
10.6.1.39
MSI Message Control Register
10.6.1.40
MSI Message Lower Address Register
10.6.1.41
MSI Message Upper Address Register
10.6.1.42
MSI Message Data Register
10.6.1.43
SSID/SSVID Capability ID Register
10.6.1.44
Next Item Pointer Register
10.6.1.45
Subsystem Vendor ID Register
10.6.1.46
Subsystem ID Register
10.6.1.47
PCI Express Capability ID Register
10.6.1.48
Next Item Pointer Register
10.6.1.49
PCI Express Capabilities Register
10.6.1.50
Device Capabilities Register
10.6.1.51
Device Control Register
10.6.1.52
Device Status Register
10.6.1.53
Link Capabilities Register
10.6.1.54
Link Control Register
10.6.1.55
Link Status Register
10.6.1.56
Serial-Bus Data Register
10.6.1.57
Serial-Bus Word Address Register
10.6.1.58
Serial-Bus Slave Address Register
10.6.1.59
Serial-Bus Control and Status Register
10.6.1.60
GPIO Control Register
10.6.1.61
GPIO Data Register
10.6.1.62
Control and Diagnostic Register 0
10.6.1.63
Control and Diagnostic Register 1
10.6.1.64
PHY Control and Diagnostic Register 2
10.6.1.65
Subsystem Access Register
10.6.1.66
General Control Register
10.6.1.67
TI Proprietary Register
10.6.1.68
TI Proprietary Register
10.6.1.69
TI Proprietary Register
10.6.1.70
Arbiter Control Register
10.6.1.71
Arbiter Request Mask Register
10.6.1.72
Arbiter Time-Out Status Register
10.6.1.73
TI Proprietary Register
10.6.1.74
TI Proprietary Register
10.6.1.75
TI Proprietary Register
10.6.2
PCIe Extended Configuration Space
10.6.2.1
Advanced Error Reporting Capability ID Register
10.6.2.2
Next Capability Offset/Capability Version Register
10.6.2.3
Uncorrectable Error Status Register
10.6.2.4
Uncorrectable Error Mask Register
10.6.2.5
Uncorrectable Error Severity Register
10.6.2.6
Correctable Error Status Register
10.6.2.7
Correctable Error Mask Register
10.6.2.8
Advanced Error Capabilities and Control Register
10.6.2.9
Header Log Register
10.6.2.10
Secondary Uncorrectable Error Status Register
10.6.2.11
Secondary Uncorrectable Error Mask Register
10.6.2.12
Secondary Uncorrectable Error Severity
10.6.2.13
Secondary Error Capabilities and Control Register
10.6.2.14
Secondary Header Log Register
10.6.3
Memory-Mapped TI Proprietary Register Space
10.6.3.1
Device Control Map ID Register
10.6.3.2
Revision ID Register
10.6.3.3
GPIO Control Register
10.6.3.4
GPIO Data Register
10.6.3.5
Serial-Bus Data Register
10.6.3.6
Serial-Bus Word Address Register
10.6.3.7
Serial-Bus Slave Address Register
10.6.3.8
Serial-Bus Control and Status Register
10.6.4
1394 OHCI PCI Configuration Space
10.6.4.1
Vendor ID Register
10.6.4.2
Device ID Register
10.6.4.3
Command Register
10.6.4.4
Status Register
10.6.4.5
Class Code and Revision ID Registers
10.6.4.6
Cache Line Size and Latency Timer Registers
10.6.4.7
Header Type and BIST Registers
10.6.4.8
OHCI Base Address Register
10.6.4.9
TI Extension Base Address Register
10.6.4.10
CIS Base Address Register
10.6.4.11
CIS Pointer Register
10.6.4.12
Subsystem Vendor ID and Subsystem ID Registers
10.6.4.13
Power Management Capabilities Pointer Register
10.6.4.14
Interrupt Line and Interrupt Pin Registers
10.6.4.15
Minimum Grant and Minimum Latency Registers
10.6.4.16
OHCI Control Register
10.6.4.17
Capability ID and Next Item Pointer Registers
10.6.4.18
Power Management Capabilities Register
10.6.4.19
Power Management Control and Status Register
10.6.4.20
Power Management Extension Registers
10.6.4.21
PCI Miscellaneous Configuration Register
10.6.4.22
Link Enhancement Control Register
10.6.4.23
Subsystem Access Register
10.6.5
1394 OHCI Memory-Mapped Register Space
10.6.5.1
OHCI Version Register
10.6.5.2
GUID ROM Register
10.6.5.3
Asynchronous Transmit Retries Register
10.6.5.4
CSR Data Register
10.6.5.5
CSR Compare Register
10.6.5.6
CSR Control Register
10.6.5.7
Configuration ROM Header Register
10.6.5.8
Bus Identification Register
10.6.5.9
Bus Options Register
10.6.5.10
GUID High Register
10.6.5.11
GUID Low Register
10.6.5.12
Configuration ROM Mapping Register
10.6.5.13
Posted Write Address Low Register
10.6.5.14
Posted Write Address High Register
10.6.5.15
Vendor ID Register
10.6.5.16
Host Controller Control Register
10.6.5.17
Self-ID Buffer Pointer Register
10.6.5.18
Self-ID Count Register
10.6.5.19
Isochronous Receive Channel Mask High Register
10.6.5.20
Isochronous Receive Channel Mask Low Register
10.6.5.21
Interrupt Event Register
10.6.5.22
Interrupt Mask Register
10.6.5.23
Isochronous Transmit Interrupt Event Register
10.6.5.24
Isochronous Transmit Interrupt Mask Register
10.6.5.25
Isochronous Receive Interrupt Event Register
10.6.5.26
Isochronous Receive Interrupt Mask Register
10.6.5.27
Initial Bandwidth Available Register
10.6.5.28
Initial Channels Available High Register
10.6.5.29
Initial Channels Available Low Register
10.6.5.30
Fairness Control Register
10.6.5.31
Link Control Register
10.6.5.32
Node Identification Register
10.6.5.33
PHY Control Register
10.6.5.34
Isochronous Cycle Timer Register
10.6.5.35
Asynchronous Request Filter High Register
10.6.5.36
Asynchronous Request Filter Low Register
10.6.5.37
Physical Request Filter High Register
10.6.5.38
Physical Request Filter Low Register
10.6.5.39
Physical Upper Bound Register (Optional Register)
10.6.5.40
Asynchronous Context Control Register
10.6.5.41
Asynchronous Context Command Pointer Register
10.6.5.42
Isochronous Transmit Context Control Register
10.6.5.43
Isochronous Transmit Context Command Pointer Register
10.6.5.44
Isochronous Receive Context Control Register
10.6.5.45
Isochronous Receive Context Command Pointer Register
10.6.5.46
Isochronous Receive Context Match Register
10.6.6
1394 OHCI Memory-Mapped TI Extension Register Space
10.6.6.1
Digital Video (DV) and MPEG2 Timestamp Enhancements
10.6.6.2
Isochronous Receive Digital Video Enhancements
10.6.6.3
Isochronous Receive Digital Video Enhancement Registers
10.6.6.4
Link Enhancement Control Registers
10.6.6.5
Timestamp Offset Registers
11
Application and Implementation
11.1
Known exceptions to functional specification (errata).
11.1.1
Errata # 1: UR bit incorrectly set in the uncorrectable error status register when the ANFES bit is set
11.1.1.1
Detailed Description
11.1.1.2
Overall Impact
11.1.1.3
Workaround Proposal
11.1.1.4
Corrective Action
11.1.2
Errata #2: File Transfer Fails When L1 is Enabled
11.1.2.1
Detailed Description
11.1.2.2
Overall Impact
11.1.2.3
Workaround Proposal
11.1.2.4
Corrective Action
11.2
Application Information
11.2.1
Typical Application
11.2.2
Application Curves
11.2.3
Design Requirements
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
14
Device and Documentation Support
14.1
Device Support
14.1.1
Device Nomenclature
14.1.1.1
Documents Conventions
14.2
Documentation Support
14.2.1
Related Documentation
14.3
Receiving Notification of Documentation Updates
14.4
支持资源
14.5
Trademarks
14.6
静电放电警告
14.7
术语表
15
Mechanical, Packaging, and Orderable Information
15.1
Mechanical Data
封装选项
机械数据 (封装 | 引脚)
PZT|100
MTQF012B
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcss38_oa
Data Sheet
TSB82AF15-EP 基于 PCI Express 的 IEEE 1394b OHCI 主机控制器