ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one is detected, bit 3 (SBDETECT) in the serial-bus control and status register (see Section 10.6.1.59) is set. Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external EEPROM is required, the serial-bus interface is permanently disabled by attaching a pulldown resistor to the SDA signal.
The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal (SDA). The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 10-6 shows an example application implementing the two-wire serial bus.