ZHCSS38 july   2020 TSB82AF15-EP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 PCIe Differential Transmitter Output Ranges
    6. 6.6 PCIe Differential Receiver Input Ranges
    7. 6.7 PCIe Differential Reference Clock Input Ranges
    8. 6.8 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)
    9. 6.9 Switching Characteristics
  8. 7 Operating Life Deration
  9. 8 Typical Characteristics
  10. 9 Parameter Measurement Information
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Power-Up/Power-Down Sequencing
        1. 10.3.1.1 Power-Up Sequence
        2. 10.3.1.2 Power-Down Sequence
      2. 10.3.2 TSB82AF15-EP Reset Features
      3. 10.3.3 PCI Express (PCIe) Interface
        1. 10.3.3.1 External Reference Clock
        2. 10.3.3.2 Beacon and Wake
        3. 10.3.3.3 Initial Flow Control Credits
        4. 10.3.3.4 PCIe Message Transactions
      4. 10.3.4 PCI Interrupt Conversion to PCIe Messages
      5. 10.3.5 Two-Wire Serial-Bus Interface
        1. 10.3.5.1 Serial-Bus Interface Implementation
        2. 10.3.5.2 Serial-Bus Interface Protocol
        3. 10.3.5.3 Serial-Bus EEPROM Application
        4. 10.3.5.4 Accessing Serial-Bus Devices Through Software
      6. 10.3.6 General-Purpose I/O (GPIO) Interface
    4. 10.4 Device Functional Modes
      1. 10.4.1 Advanced Error Reporting Registers
      2. 10.4.2 Data Error Forwarding Capability
      3. 10.4.3 Set Slot Power Limit Functionality
      4. 10.4.4 PCIe and PCI Bus Power Management
    5. 10.5 Programming
      1. 10.5.1 1394b OHCI Controller Functionality
        1. 10.5.1.1 1394b OHCI Power Management
        2. 10.5.1.2 1394b OHCI and V AUX
        3. 10.5.1.3 1394b OHCI and Reset Options
        4. 10.5.1.4 1394b OHCI PCI Bus Master
        5. 10.5.1.5 1394b OHCI Subsystem Identification
        6. 10.5.1.6 1394b OHCI PME Support
    6. 10.6 Register Maps
      1. 10.6.1 Classic PCI Configuration Space
        1. 10.6.1.1  Vendor ID Register
        2. 10.6.1.2  Device ID Register
        3. 10.6.1.3  Command Register
        4. 10.6.1.4  Status Register
        5. 10.6.1.5  Class Code and Revision ID Register
        6. 10.6.1.6  Cache Line Size Register
        7. 10.6.1.7  Primary Latency Timer Register
        8. 10.6.1.8  Header Type Register
        9. 10.6.1.9  BIST Register
        10. 10.6.1.10 Device Control Base Address Register
        11. 10.6.1.11 Scratchpad RAM Base Address
        12. 10.6.1.12 Primary Bus Number Register
        13. 10.6.1.13 Secondary Bus Number Register
        14. 10.6.1.14 Subordinate Bus Number Register
        15. 10.6.1.15 Secondary Latency Timer Register
        16. 10.6.1.16 I/O Base Register
        17. 10.6.1.17 I/O Limit Register
        18. 10.6.1.18 Secondary Status Register
        19. 10.6.1.19 Memory Base Register
        20. 10.6.1.20 Memory Limit Register
        21. 10.6.1.21 Prefetchable Memory Base Register
        22. 10.6.1.22 Prefetchable Memory Limit Register
        23. 10.6.1.23 Prefetchable Base Upper 32 Bits Register
        24. 10.6.1.24 Prefetchable Limit Upper 32 Bits Register
        25. 10.6.1.25 I/O Base Upper 16 Bits Register
        26. 10.6.1.26 I/O Limit Upper 16 Bits Register
        27. 10.6.1.27 Capabilities Pointer Register
        28. 10.6.1.28 Interrupt Line Register
        29. 10.6.1.29 Interrupt Pin Register
        30. 10.6.1.30 Bridge Control Register
        31. 10.6.1.31 PM Capability ID Register
        32. 10.6.1.32 Next Item Pointer Register
        33. 10.6.1.33 Power Management Capabilities Register
        34. 10.6.1.34 Power Management Control/Status Register
        35. 10.6.1.35 Power Management Bridge Support Extension Register
        36. 10.6.1.36 Power Management Data Register
        37. 10.6.1.37 MSI Capability ID Register
        38. 10.6.1.38 Next Item Pointer Register
        39. 10.6.1.39 MSI Message Control Register
        40. 10.6.1.40 MSI Message Lower Address Register
        41. 10.6.1.41 MSI Message Upper Address Register
        42. 10.6.1.42 MSI Message Data Register
        43. 10.6.1.43 SSID/SSVID Capability ID Register
        44. 10.6.1.44 Next Item Pointer Register
        45. 10.6.1.45 Subsystem Vendor ID Register
        46. 10.6.1.46 Subsystem ID Register
        47. 10.6.1.47 PCI Express Capability ID Register
        48. 10.6.1.48 Next Item Pointer Register
        49. 10.6.1.49 PCI Express Capabilities Register
        50. 10.6.1.50 Device Capabilities Register
        51. 10.6.1.51 Device Control Register
        52. 10.6.1.52 Device Status Register
        53. 10.6.1.53 Link Capabilities Register
        54. 10.6.1.54 Link Control Register
        55. 10.6.1.55 Link Status Register
        56. 10.6.1.56 Serial-Bus Data Register
        57. 10.6.1.57 Serial-Bus Word Address Register
        58. 10.6.1.58 Serial-Bus Slave Address Register
        59. 10.6.1.59 Serial-Bus Control and Status Register
        60. 10.6.1.60 GPIO Control Register
        61. 10.6.1.61 GPIO Data Register
        62. 10.6.1.62 Control and Diagnostic Register 0
        63. 10.6.1.63 Control and Diagnostic Register 1
        64. 10.6.1.64 PHY Control and Diagnostic Register 2
        65. 10.6.1.65 Subsystem Access Register
        66. 10.6.1.66 General Control Register
        67. 10.6.1.67 TI Proprietary Register
        68. 10.6.1.68 TI Proprietary Register
        69. 10.6.1.69 TI Proprietary Register
        70. 10.6.1.70 Arbiter Control Register
        71. 10.6.1.71 Arbiter Request Mask Register
        72. 10.6.1.72 Arbiter Time-Out Status Register
        73. 10.6.1.73 TI Proprietary Register
        74. 10.6.1.74 TI Proprietary Register
        75. 10.6.1.75 TI Proprietary Register
      2. 10.6.2 PCIe Extended Configuration Space
        1. 10.6.2.1  Advanced Error Reporting Capability ID Register
        2. 10.6.2.2  Next Capability Offset/Capability Version Register
        3. 10.6.2.3  Uncorrectable Error Status Register
        4. 10.6.2.4  Uncorrectable Error Mask Register
        5. 10.6.2.5  Uncorrectable Error Severity Register
        6. 10.6.2.6  Correctable Error Status Register
        7. 10.6.2.7  Correctable Error Mask Register
        8. 10.6.2.8  Advanced Error Capabilities and Control Register
        9. 10.6.2.9  Header Log Register
        10. 10.6.2.10 Secondary Uncorrectable Error Status Register
        11. 10.6.2.11 Secondary Uncorrectable Error Mask Register
        12. 10.6.2.12 Secondary Uncorrectable Error Severity
        13. 10.6.2.13 Secondary Error Capabilities and Control Register
        14. 10.6.2.14 Secondary Header Log Register
      3. 10.6.3 Memory-Mapped TI Proprietary Register Space
        1. 10.6.3.1 Device Control Map ID Register
        2. 10.6.3.2 Revision ID Register
        3. 10.6.3.3 GPIO Control Register
        4. 10.6.3.4 GPIO Data Register
        5. 10.6.3.5 Serial-Bus Data Register
        6. 10.6.3.6 Serial-Bus Word Address Register
        7. 10.6.3.7 Serial-Bus Slave Address Register
        8. 10.6.3.8 Serial-Bus Control and Status Register
      4. 10.6.4 1394 OHCI PCI Configuration Space
        1. 10.6.4.1  Vendor ID Register
        2. 10.6.4.2  Device ID Register
        3. 10.6.4.3  Command Register
        4. 10.6.4.4  Status Register
        5. 10.6.4.5  Class Code and Revision ID Registers
        6. 10.6.4.6  Cache Line Size and Latency Timer Registers
        7. 10.6.4.7  Header Type and BIST Registers
        8. 10.6.4.8  OHCI Base Address Register
        9. 10.6.4.9  TI Extension Base Address Register
        10. 10.6.4.10 CIS Base Address Register
        11. 10.6.4.11 CIS Pointer Register
        12. 10.6.4.12 Subsystem Vendor ID and Subsystem ID Registers
        13. 10.6.4.13 Power Management Capabilities Pointer Register
        14. 10.6.4.14 Interrupt Line and Interrupt Pin Registers
        15. 10.6.4.15 Minimum Grant and Minimum Latency Registers
        16. 10.6.4.16 OHCI Control Register
        17. 10.6.4.17 Capability ID and Next Item Pointer Registers
        18. 10.6.4.18 Power Management Capabilities Register
        19. 10.6.4.19 Power Management Control and Status Register
        20. 10.6.4.20 Power Management Extension Registers
        21. 10.6.4.21 PCI Miscellaneous Configuration Register
        22. 10.6.4.22 Link Enhancement Control Register
        23. 10.6.4.23 Subsystem Access Register
      5. 10.6.5 1394 OHCI Memory-Mapped Register Space
        1. 10.6.5.1  OHCI Version Register
        2. 10.6.5.2  GUID ROM Register
        3. 10.6.5.3  Asynchronous Transmit Retries Register
        4. 10.6.5.4  CSR Data Register
        5. 10.6.5.5  CSR Compare Register
        6. 10.6.5.6  CSR Control Register
        7. 10.6.5.7  Configuration ROM Header Register
        8. 10.6.5.8  Bus Identification Register
        9. 10.6.5.9  Bus Options Register
        10. 10.6.5.10 GUID High Register
        11. 10.6.5.11 GUID Low Register
        12. 10.6.5.12 Configuration ROM Mapping Register
        13. 10.6.5.13 Posted Write Address Low Register
        14. 10.6.5.14 Posted Write Address High Register
        15. 10.6.5.15 Vendor ID Register
        16. 10.6.5.16 Host Controller Control Register
        17. 10.6.5.17 Self-ID Buffer Pointer Register
        18. 10.6.5.18 Self-ID Count Register
        19. 10.6.5.19 Isochronous Receive Channel Mask High Register
        20. 10.6.5.20 Isochronous Receive Channel Mask Low Register
        21. 10.6.5.21 Interrupt Event Register
        22. 10.6.5.22 Interrupt Mask Register
        23. 10.6.5.23 Isochronous Transmit Interrupt Event Register
        24. 10.6.5.24 Isochronous Transmit Interrupt Mask Register
        25. 10.6.5.25 Isochronous Receive Interrupt Event Register
        26. 10.6.5.26 Isochronous Receive Interrupt Mask Register
        27. 10.6.5.27 Initial Bandwidth Available Register
        28. 10.6.5.28 Initial Channels Available High Register
        29. 10.6.5.29 Initial Channels Available Low Register
        30. 10.6.5.30 Fairness Control Register
        31. 10.6.5.31 Link Control Register
        32. 10.6.5.32 Node Identification Register
        33. 10.6.5.33 PHY Control Register
        34. 10.6.5.34 Isochronous Cycle Timer Register
        35. 10.6.5.35 Asynchronous Request Filter High Register
        36. 10.6.5.36 Asynchronous Request Filter Low Register
        37. 10.6.5.37 Physical Request Filter High Register
        38. 10.6.5.38 Physical Request Filter Low Register
        39. 10.6.5.39 Physical Upper Bound Register (Optional Register)
        40. 10.6.5.40 Asynchronous Context Control Register
        41. 10.6.5.41 Asynchronous Context Command Pointer Register
        42. 10.6.5.42 Isochronous Transmit Context Control Register
        43. 10.6.5.43 Isochronous Transmit Context Command Pointer Register
        44. 10.6.5.44 Isochronous Receive Context Control Register
        45. 10.6.5.45 Isochronous Receive Context Command Pointer Register
        46. 10.6.5.46 Isochronous Receive Context Match Register
      6. 10.6.6 1394 OHCI Memory-Mapped TI Extension Register Space
        1. 10.6.6.1 Digital Video (DV) and MPEG2 Timestamp Enhancements
        2. 10.6.6.2 Isochronous Receive Digital Video Enhancements
        3. 10.6.6.3 Isochronous Receive Digital Video Enhancement Registers
        4. 10.6.6.4 Link Enhancement Control Registers
        5. 10.6.6.5 Timestamp Offset Registers
  12. 11Application and Implementation
    1. 11.1 Known exceptions to functional specification (errata).
      1. 11.1.1 Errata # 1: UR bit incorrectly set in the uncorrectable error status register when the ANFES bit is set
        1. 11.1.1.1 Detailed Description
        2. 11.1.1.2 Overall Impact
        3. 11.1.1.3 Workaround Proposal
        4. 11.1.1.4 Corrective Action
      2. 11.1.2 Errata #2: File Transfer Fails When L1 is Enabled
        1. 11.1.2.1 Detailed Description
        2. 11.1.2.2 Overall Impact
        3. 11.1.2.3 Workaround Proposal
        4. 11.1.2.4 Corrective Action
    2. 11.2 Application Information
      1. 11.2.1 Typical Application
      2. 11.2.2 Application Curves
      3. 11.2.3 Design Requirements
  13. 12Power Supply Recommendations
  14. 13Layout
    1. 13.1 Layout Guidelines
  15. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
        1. 14.1.1.1 Documents Conventions
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 支持资源
    5. 14.5 Trademarks
    6. 14.6 静电放电警告
    7. 14.7 术语表
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Mechanical Data

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订购信息

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
REFCLK+ 1 DI Reference clock positive. REFCLK+ and REFCLK- comprise the differential input pair for the 100-MHz system reference clock.
REFCLK- 2 DI Reference clock negative. REFCLK+ and REFCLK- comprise the differential input pair for the 100-MHz system reference clock.
VSSA 3 P Analog ground.
VDD_33 4 P 3.3-V digital I/O power. Filter from VDDA_33 supply.
LPS 5 O Link power status. This terminal must be connected to the LPS input terminal of the connected PHY.
PINT 6 I PHY interrupt. The connected PHY uses this signal to transfer status and interrupt information serially to the LLC. This terminal must be connected to the PINT output of the connected PHY.
LINKON 7 I/O Link-on notification. LINKON is an input to the LLC from the connected PHY that is used to provide notification that a link-on packet has been received or an event, such as a port connection, has occurred. This I/O only has meaning when LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If LINKON becomes active in the D0 (uninitialized), D2, or D3 power state, the TSB82AF15-EP device sets bit 15 (PME_STS) in the power-management control and status register in the PCI configuration space at offset 48h. This terminal must be connected to the LKON output terminal of the connected PHY.
LREQ 8 O LLC request. The LLC uses this output to initiate a service request to the connected PHY. This terminal must be connected to the LREQ input of the connected PHY.
VSS 9 P Digital ground.
PCLK 10 I PHY clock. This terminal must be connected to the PCLK output of the connected PHY.
VDD_15 11 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
LCLK 12 O LLC clock. This terminal must be connected to the LCLK input terminal of the connected PHY.
VDD_33 13 P 3.3-V digital I/O power. Filter from VDDA_33 supply.
CTL0 14 I/O Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the phase of operation of the PHY link interface. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these terminals should be left unconnected.
CTL1 15 I/O Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the phase of operation of the PHY link interface. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on CTL[1:0] is synchronous to PCLK. When driven by the link, information on CTL[1:0] is synchronous to LCLK. If not implemented, these terminals should be left unconnected.
VSS 16 P Digital ground.
D0 17 I/O Data. D[7:0] comprise a bidirectional data bus that is used to carry 1394 packet data, packet speed, and grant type information between the PHY and the link. Upon a reset of the interface, this bus is driven by the PHY. When driven by the PHY, information on D[7:0] is synchronous to PCLK. When driven by the link, information on D[7:0] is synchronous to LCLK. If not implemented, these terminals should be left unconnected.
D1 18 I/O D1
D2 19 I/O D2
VDD_15 20 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
D3 21 I/O D3
D4 22 I/O D4
D5 23 I/O D5
VSS 24 P Digital ground.
D6 25 I/O D6
D7 26 I/O D7
VDD_33 27 P 3.3-V digital I/O power. Filter from VDDA_33 supply.
GPIO0 28 I/O General-purpose I/O 0. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
GPIO1 29 I/O General-purpose I/O 1. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
GPIO2 30 I/O General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
VSS 31 P Digital ground.
GPIO3 32 I/O General-purpose I/O 3. This terminal functions as a GPIO controlled by bit 3 (GPIO3_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
GPIO4 33 I/O General-purpose I/O 4. This terminal functions as a GPIO controlled by bit 4 (GPIO4_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
GPIO5 34 I/O General-purpose I/O 5. This terminal functions as a GPIO controlled by bit 5 (GPIO5_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
GPIO6 35 I/O General-purpose I/O 6. This terminal functions as a GPIO controlled by bit 6 (GPIO6_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
VDD_15 36 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
GPIO7 37 I/O General-purpose I/O 7. This terminal functions as a GPIO controlled by bit 7 (GPIO7_DIR) in the GPIO control register (See Section 10.6.1.60). Note: This terminal has an internal active pullup resistor.
VDD_15 38 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
OHCI_PME# 39 O OHCI power-management event. This is an optional signal that can be used by a device to request a change in the device or system power state. This signal must be enabled by software.
VSS 40 P Digital ground.
CYCLEOUT 41 O Cycle out. This terminal provides an 8-kHz cycle timer synchronization signal. If not implemented, this terminal should be left unconnected.
RSVD_VSS 42 I Reserved pin, connect to VSS.
RSVD 43 O Reserved pin, leave unconnected.
VDD_33 44 P 3.3-V digital I/O power. Filter from VDDA_33 supply.
RSVD 45 O Reserved pin, leave unconnected.
RSVD 46 O Reserved pin, leave unconnected.
RSVD 47 O Reserved pin, leave unconnected.
VSS 48 P Digital ground.
RSVD 49 O Reserved pin, leave unconnected.
RSVD 50 O Reserved pin, leave unconnected.
RSVD 51 O Reserved pin, leave unconnected.
RSVD 52 O Reserved pin, leave unconnected.
VDD_15 53 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
RSVD 54 O Reserved pin, leave unconnected.
RSVD 55 O Reserved pin, leave unconnected.
RSVD 56 O Reserved pin, leave unconnected.
VDD_33 57 P 3.3-V digital I/O power. Filter from VDDA_33 supply.
RSVD 58 O Reserved pin, leave unconnected.
CLKREQ 59 O Clock request. This terminal is used to support the clock request protocol. Note: CLKREQ is an open-drain output buffer. An external pullup resistor is required, even if CLKREQ functionality is unused.
VSS 60 P Digital ground.
SCL 61 I/O Serial-bus clock. This signal is used as a serial bus clock when a pullup is detected on SDA or when the SBDETECT bit is set in the serial bus control and status register. Note: This terminal has an internal active pullup resistor.
SDA 62 I/O Serial-bus data. This signal is used as serial bus data when a pullup is detected on SDA or when the SBDETECT bit is set in the serial bus control and status register. Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA signal from floating.
REFCLK_SEL 63 I Reference clock select. This terminal selects the reference clock input. 0 = 100-MHz differential common reference clock used. REFCLK_SEL must be driven logic low to enable 100Mhz differential clock. 125Mhz single ended clocking is not supported.
VDD_15 64 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
RSVD_VSS 65 I Reserved Pin, connect to VSS.
RSVD 66 O Reserved pin, leave unconnected.
RSVD 67 O Reserved pin, leave unconnected.
VSS 68 P Digital ground.
RSVD 69 O Reserved pin, leave unconnected.
RSVD_VSS 70 I Reserved Pin, connect to VSS.
RSVD_VSS 71 I Reserved Pin, connect to VSS.
VDD_33 72 P 3.3-V digital I/O power. Filter from VDDA_33 supply.
GRST 73 I Global power reset. This reset brings all of the TSB82AF15-EP internal link registers to their default states. This should be a one-time power-on reset. This terminal has hysteresis and an integrated pullup resistor.
PERST 74 I PCI Express reset. PERST identifies when the system power is stable and generates an internal power-on reset. Note: The PERST input buffer has hysteresis.
VSS 75 P Digital ground.
VDD_15_COMB 76 P Internal 1.5-V main power output for external bypass capacitor filtering. Caution: Do not use this terminal to supply external power to other devices.
VDD_33_COMBIO 77 P Internal 3.3-V IO power output for external bypass capacitor filtering. Caution: Do not use this terminal to supply external power to other devices.
VSSA 78 P Analog ground.
REF0_PCIE 79 I/O External reference resistor + and – terminals for setting TX driver current. An external resistance of 14.532kΩ is connected between REF0_PCIE and REF1_PCIE terminals. To eliminate the need for a custom resistor, two series resistors are recommended: a 14.3kΩ, 1% resistor and a 232Ω, 1% resistor.
REF1_PCIE 80 I/O
VSS 81 P Digital ground.
VDD_33_AUX 82 P This terminal is connected to VSS through a 10kΩ pulldown resistor. The TSB82AF15-EP does not support auxiliary power.
VDDA_33 83 P 3.3-V digital I/O power for the link. Filter from VDD_33 supply.
VDD_33_COMB 84 P Internal 3.3-V main power output for external bypass capacitor filtering. Caution: Do not use this terminal to supply external power to other devices.
VDDA_15 85 P 1.5-V analog power for the link. Filter from VDD_15 supply.
VDDA_15 86 P 1.5-V analog power for the link. Filter from VDD_15 supply.
VSSA_PCIE 87 P Analog ground for PCIe function.
TXP 88 DO High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single PCIe lane.
TXN 89 DO High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single PCIe lane
VSSA_PCIE 90 P Analog ground for PCIe function.
VDD_15 91 P 1.5-V digital core power for the link. Filter from VDDA_15 supply.
VSS_PCIE 92 P Digital ground for PCIe function.
VDDA_15 93 P 1.5-V analog power for the link. Filter from VDD_15 supply.
VSSA 94 P Analog ground.
VDDA_15 95 P 1.5-V analog power for the link. Filter from VDD_15 supply.
VSSA_PCIE 96 P Analog ground for PCIe function.
RXP 97 DI High-speed receive pair. RXP and RXN comprise the differential receive pair for the single PCIe lane.
RXN 98 DI High-speed receive pair. RXP and RXN comprise the differential receive pair for the single PCIe lane.
VSSA_PCIE 99 P Analog ground for PCIe function.
VDDA_33 100 P 3.3-V digital I/O power for the link. Filter from VDD_33 supply.
(1)
  • Pin Type Legend:
    • DI: Differential Input
    • DO: Differential Output
    • I: Input pin
    • O: Output pin
    • I/O: Pin can be Input or Output depending on configuration
    • P: Power Supply or Ground