ZHCSS38 july   2020 TSB82AF15-EP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 PCIe Differential Transmitter Output Ranges
    6. 6.6 PCIe Differential Receiver Input Ranges
    7. 6.7 PCIe Differential Reference Clock Input Ranges
    8. 6.8 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)
    9. 6.9 Switching Characteristics
  8. 7 Operating Life Deration
  9. 8 Typical Characteristics
  10. 9 Parameter Measurement Information
  11. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Power-Up/Power-Down Sequencing
        1. 10.3.1.1 Power-Up Sequence
        2. 10.3.1.2 Power-Down Sequence
      2. 10.3.2 TSB82AF15-EP Reset Features
      3. 10.3.3 PCI Express (PCIe) Interface
        1. 10.3.3.1 External Reference Clock
        2. 10.3.3.2 Beacon and Wake
        3. 10.3.3.3 Initial Flow Control Credits
        4. 10.3.3.4 PCIe Message Transactions
      4. 10.3.4 PCI Interrupt Conversion to PCIe Messages
      5. 10.3.5 Two-Wire Serial-Bus Interface
        1. 10.3.5.1 Serial-Bus Interface Implementation
        2. 10.3.5.2 Serial-Bus Interface Protocol
        3. 10.3.5.3 Serial-Bus EEPROM Application
        4. 10.3.5.4 Accessing Serial-Bus Devices Through Software
      6. 10.3.6 General-Purpose I/O (GPIO) Interface
    4. 10.4 Device Functional Modes
      1. 10.4.1 Advanced Error Reporting Registers
      2. 10.4.2 Data Error Forwarding Capability
      3. 10.4.3 Set Slot Power Limit Functionality
      4. 10.4.4 PCIe and PCI Bus Power Management
    5. 10.5 Programming
      1. 10.5.1 1394b OHCI Controller Functionality
        1. 10.5.1.1 1394b OHCI Power Management
        2. 10.5.1.2 1394b OHCI and V AUX
        3. 10.5.1.3 1394b OHCI and Reset Options
        4. 10.5.1.4 1394b OHCI PCI Bus Master
        5. 10.5.1.5 1394b OHCI Subsystem Identification
        6. 10.5.1.6 1394b OHCI PME Support
    6. 10.6 Register Maps
      1. 10.6.1 Classic PCI Configuration Space
        1. 10.6.1.1  Vendor ID Register
        2. 10.6.1.2  Device ID Register
        3. 10.6.1.3  Command Register
        4. 10.6.1.4  Status Register
        5. 10.6.1.5  Class Code and Revision ID Register
        6. 10.6.1.6  Cache Line Size Register
        7. 10.6.1.7  Primary Latency Timer Register
        8. 10.6.1.8  Header Type Register
        9. 10.6.1.9  BIST Register
        10. 10.6.1.10 Device Control Base Address Register
        11. 10.6.1.11 Scratchpad RAM Base Address
        12. 10.6.1.12 Primary Bus Number Register
        13. 10.6.1.13 Secondary Bus Number Register
        14. 10.6.1.14 Subordinate Bus Number Register
        15. 10.6.1.15 Secondary Latency Timer Register
        16. 10.6.1.16 I/O Base Register
        17. 10.6.1.17 I/O Limit Register
        18. 10.6.1.18 Secondary Status Register
        19. 10.6.1.19 Memory Base Register
        20. 10.6.1.20 Memory Limit Register
        21. 10.6.1.21 Prefetchable Memory Base Register
        22. 10.6.1.22 Prefetchable Memory Limit Register
        23. 10.6.1.23 Prefetchable Base Upper 32 Bits Register
        24. 10.6.1.24 Prefetchable Limit Upper 32 Bits Register
        25. 10.6.1.25 I/O Base Upper 16 Bits Register
        26. 10.6.1.26 I/O Limit Upper 16 Bits Register
        27. 10.6.1.27 Capabilities Pointer Register
        28. 10.6.1.28 Interrupt Line Register
        29. 10.6.1.29 Interrupt Pin Register
        30. 10.6.1.30 Bridge Control Register
        31. 10.6.1.31 PM Capability ID Register
        32. 10.6.1.32 Next Item Pointer Register
        33. 10.6.1.33 Power Management Capabilities Register
        34. 10.6.1.34 Power Management Control/Status Register
        35. 10.6.1.35 Power Management Bridge Support Extension Register
        36. 10.6.1.36 Power Management Data Register
        37. 10.6.1.37 MSI Capability ID Register
        38. 10.6.1.38 Next Item Pointer Register
        39. 10.6.1.39 MSI Message Control Register
        40. 10.6.1.40 MSI Message Lower Address Register
        41. 10.6.1.41 MSI Message Upper Address Register
        42. 10.6.1.42 MSI Message Data Register
        43. 10.6.1.43 SSID/SSVID Capability ID Register
        44. 10.6.1.44 Next Item Pointer Register
        45. 10.6.1.45 Subsystem Vendor ID Register
        46. 10.6.1.46 Subsystem ID Register
        47. 10.6.1.47 PCI Express Capability ID Register
        48. 10.6.1.48 Next Item Pointer Register
        49. 10.6.1.49 PCI Express Capabilities Register
        50. 10.6.1.50 Device Capabilities Register
        51. 10.6.1.51 Device Control Register
        52. 10.6.1.52 Device Status Register
        53. 10.6.1.53 Link Capabilities Register
        54. 10.6.1.54 Link Control Register
        55. 10.6.1.55 Link Status Register
        56. 10.6.1.56 Serial-Bus Data Register
        57. 10.6.1.57 Serial-Bus Word Address Register
        58. 10.6.1.58 Serial-Bus Slave Address Register
        59. 10.6.1.59 Serial-Bus Control and Status Register
        60. 10.6.1.60 GPIO Control Register
        61. 10.6.1.61 GPIO Data Register
        62. 10.6.1.62 Control and Diagnostic Register 0
        63. 10.6.1.63 Control and Diagnostic Register 1
        64. 10.6.1.64 PHY Control and Diagnostic Register 2
        65. 10.6.1.65 Subsystem Access Register
        66. 10.6.1.66 General Control Register
        67. 10.6.1.67 TI Proprietary Register
        68. 10.6.1.68 TI Proprietary Register
        69. 10.6.1.69 TI Proprietary Register
        70. 10.6.1.70 Arbiter Control Register
        71. 10.6.1.71 Arbiter Request Mask Register
        72. 10.6.1.72 Arbiter Time-Out Status Register
        73. 10.6.1.73 TI Proprietary Register
        74. 10.6.1.74 TI Proprietary Register
        75. 10.6.1.75 TI Proprietary Register
      2. 10.6.2 PCIe Extended Configuration Space
        1. 10.6.2.1  Advanced Error Reporting Capability ID Register
        2. 10.6.2.2  Next Capability Offset/Capability Version Register
        3. 10.6.2.3  Uncorrectable Error Status Register
        4. 10.6.2.4  Uncorrectable Error Mask Register
        5. 10.6.2.5  Uncorrectable Error Severity Register
        6. 10.6.2.6  Correctable Error Status Register
        7. 10.6.2.7  Correctable Error Mask Register
        8. 10.6.2.8  Advanced Error Capabilities and Control Register
        9. 10.6.2.9  Header Log Register
        10. 10.6.2.10 Secondary Uncorrectable Error Status Register
        11. 10.6.2.11 Secondary Uncorrectable Error Mask Register
        12. 10.6.2.12 Secondary Uncorrectable Error Severity
        13. 10.6.2.13 Secondary Error Capabilities and Control Register
        14. 10.6.2.14 Secondary Header Log Register
      3. 10.6.3 Memory-Mapped TI Proprietary Register Space
        1. 10.6.3.1 Device Control Map ID Register
        2. 10.6.3.2 Revision ID Register
        3. 10.6.3.3 GPIO Control Register
        4. 10.6.3.4 GPIO Data Register
        5. 10.6.3.5 Serial-Bus Data Register
        6. 10.6.3.6 Serial-Bus Word Address Register
        7. 10.6.3.7 Serial-Bus Slave Address Register
        8. 10.6.3.8 Serial-Bus Control and Status Register
      4. 10.6.4 1394 OHCI PCI Configuration Space
        1. 10.6.4.1  Vendor ID Register
        2. 10.6.4.2  Device ID Register
        3. 10.6.4.3  Command Register
        4. 10.6.4.4  Status Register
        5. 10.6.4.5  Class Code and Revision ID Registers
        6. 10.6.4.6  Cache Line Size and Latency Timer Registers
        7. 10.6.4.7  Header Type and BIST Registers
        8. 10.6.4.8  OHCI Base Address Register
        9. 10.6.4.9  TI Extension Base Address Register
        10. 10.6.4.10 CIS Base Address Register
        11. 10.6.4.11 CIS Pointer Register
        12. 10.6.4.12 Subsystem Vendor ID and Subsystem ID Registers
        13. 10.6.4.13 Power Management Capabilities Pointer Register
        14. 10.6.4.14 Interrupt Line and Interrupt Pin Registers
        15. 10.6.4.15 Minimum Grant and Minimum Latency Registers
        16. 10.6.4.16 OHCI Control Register
        17. 10.6.4.17 Capability ID and Next Item Pointer Registers
        18. 10.6.4.18 Power Management Capabilities Register
        19. 10.6.4.19 Power Management Control and Status Register
        20. 10.6.4.20 Power Management Extension Registers
        21. 10.6.4.21 PCI Miscellaneous Configuration Register
        22. 10.6.4.22 Link Enhancement Control Register
        23. 10.6.4.23 Subsystem Access Register
      5. 10.6.5 1394 OHCI Memory-Mapped Register Space
        1. 10.6.5.1  OHCI Version Register
        2. 10.6.5.2  GUID ROM Register
        3. 10.6.5.3  Asynchronous Transmit Retries Register
        4. 10.6.5.4  CSR Data Register
        5. 10.6.5.5  CSR Compare Register
        6. 10.6.5.6  CSR Control Register
        7. 10.6.5.7  Configuration ROM Header Register
        8. 10.6.5.8  Bus Identification Register
        9. 10.6.5.9  Bus Options Register
        10. 10.6.5.10 GUID High Register
        11. 10.6.5.11 GUID Low Register
        12. 10.6.5.12 Configuration ROM Mapping Register
        13. 10.6.5.13 Posted Write Address Low Register
        14. 10.6.5.14 Posted Write Address High Register
        15. 10.6.5.15 Vendor ID Register
        16. 10.6.5.16 Host Controller Control Register
        17. 10.6.5.17 Self-ID Buffer Pointer Register
        18. 10.6.5.18 Self-ID Count Register
        19. 10.6.5.19 Isochronous Receive Channel Mask High Register
        20. 10.6.5.20 Isochronous Receive Channel Mask Low Register
        21. 10.6.5.21 Interrupt Event Register
        22. 10.6.5.22 Interrupt Mask Register
        23. 10.6.5.23 Isochronous Transmit Interrupt Event Register
        24. 10.6.5.24 Isochronous Transmit Interrupt Mask Register
        25. 10.6.5.25 Isochronous Receive Interrupt Event Register
        26. 10.6.5.26 Isochronous Receive Interrupt Mask Register
        27. 10.6.5.27 Initial Bandwidth Available Register
        28. 10.6.5.28 Initial Channels Available High Register
        29. 10.6.5.29 Initial Channels Available Low Register
        30. 10.6.5.30 Fairness Control Register
        31. 10.6.5.31 Link Control Register
        32. 10.6.5.32 Node Identification Register
        33. 10.6.5.33 PHY Control Register
        34. 10.6.5.34 Isochronous Cycle Timer Register
        35. 10.6.5.35 Asynchronous Request Filter High Register
        36. 10.6.5.36 Asynchronous Request Filter Low Register
        37. 10.6.5.37 Physical Request Filter High Register
        38. 10.6.5.38 Physical Request Filter Low Register
        39. 10.6.5.39 Physical Upper Bound Register (Optional Register)
        40. 10.6.5.40 Asynchronous Context Control Register
        41. 10.6.5.41 Asynchronous Context Command Pointer Register
        42. 10.6.5.42 Isochronous Transmit Context Control Register
        43. 10.6.5.43 Isochronous Transmit Context Command Pointer Register
        44. 10.6.5.44 Isochronous Receive Context Control Register
        45. 10.6.5.45 Isochronous Receive Context Command Pointer Register
        46. 10.6.5.46 Isochronous Receive Context Match Register
      6. 10.6.6 1394 OHCI Memory-Mapped TI Extension Register Space
        1. 10.6.6.1 Digital Video (DV) and MPEG2 Timestamp Enhancements
        2. 10.6.6.2 Isochronous Receive Digital Video Enhancements
        3. 10.6.6.3 Isochronous Receive Digital Video Enhancement Registers
        4. 10.6.6.4 Link Enhancement Control Registers
        5. 10.6.6.5 Timestamp Offset Registers
  12. 11Application and Implementation
    1. 11.1 Known exceptions to functional specification (errata).
      1. 11.1.1 Errata # 1: UR bit incorrectly set in the uncorrectable error status register when the ANFES bit is set
        1. 11.1.1.1 Detailed Description
        2. 11.1.1.2 Overall Impact
        3. 11.1.1.3 Workaround Proposal
        4. 11.1.1.4 Corrective Action
      2. 11.1.2 Errata #2: File Transfer Fails When L1 is Enabled
        1. 11.1.2.1 Detailed Description
        2. 11.1.2.2 Overall Impact
        3. 11.1.2.3 Workaround Proposal
        4. 11.1.2.4 Corrective Action
    2. 11.2 Application Information
      1. 11.2.1 Typical Application
      2. 11.2.2 Application Curves
      3. 11.2.3 Design Requirements
  13. 12Power Supply Recommendations
  14. 13Layout
    1. 13.1 Layout Guidelines
  15. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
        1. 14.1.1.1 Documents Conventions
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Receiving Notification of Documentation Updates
    4. 14.4 支持资源
    5. 14.5 Trademarks
    6. 14.6 静电放电警告
    7. 14.7 术语表
  16. 15Mechanical, Packaging, and Orderable Information
    1. 15.1 Mechanical Data

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10.6.5 1394 OHCI Memory-Mapped Register Space

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 10.6.4.8). These registers are the primary interface for controlling the IEEE Std 1394 link function.

This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming model are implemented to solve various issues with typical read-modify-write control registers. There are two addresses for a set/clear register — RegisterSet and RegisterClear (see Table 10-88 for register listing). A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set to 1b; a 0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared; a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively. However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt event register is an example of this behavior.

Table 10-88 OHCI Register Map
DMA CONTEXTREGISTER NAMEABBREVIATIONOFFSET
OHCI versionVersion00h
GUID ROMGUID_ROM04h
Asynchronous transmit retriesATRetries08h
CSR dataCSRData0Ch
CSR compareCSRCompareData10h
CSR controlCSRControl14h
Configuration ROM headerConfigROMhdr18h
Bus identificationBusID1Ch
Bus options(1)BusOptions20h
GUID high(1)GUIDHi24h
GUID low(1)GUIDLo28h
Reserved(1)2Ch-30h
Configuration ROM mappingConfigROMmap34h
Posted write address lowPostedWriteAddressLo38h
Posted write address highPostedWriteAddressHi3Ch
Vendor IDVendorID40h
Reserved44h-4Ch
Host controller control (1)HCControlSet50h
HCControlClr54h
Reserved58h-5Ch
Self-IDReserved60h
Self-ID buffer pointerSelfIDBuffer64h
Self-ID countSelfIDCount68h
Reserved6Ch
Isochronous receive channel mask highIRChannelMaskHiSet70h
IRChannelMaskHiClear74h
Isochronous receive channel mask lowIRChannelMaskLoSet78h
IRChannelMaskLoClear7Ch
Interrupt eventIntEventSet80h
IntEventClear84h
Interrupt maskIntMaskSet88h
IntMaskClear8Ch
Isochronous transmit interrupt eventIsoXmitIntEventSet90h
IsoXmitIntEventClear94h
Isochronous transmit interrupt maskIsoXmitIntMaskSet98h
IsoXmitIntMaskClear9Ch
Isochronous receive interrupt eventIsoRecvIntEventSetA0h
IsoRecvIntEventClearA4h
Isochronous receive interrupt maskIsoRecvIntMaskSetA8h
IsoRecvIntMaskClearACh
Initial bandwidth availableInitialBandwidthAvailableB0h
Initial channels available highInitialChannelsAvailableHiB4h
Initial channels available lowInitialChannelsAvailableLoB8h
ReservedBCh-D8h
Fairness controlFairnessControlDCh
Link control (1)LinkControlSetE0h
LinkControlClearE4h
Node identificationNodeIDE8h
PHY controlPhyControlECh
Isochronous cycle timerIsocyctimerF0h
ReservedF4h-FCh
Asynchronous request filter highAsyncRequestFilterHiSet100h
AsyncRequestFilterHiClear104h
Asynchronous request filter lowAsyncRequestFilterLoSet108h
AsyncRequestFilterLoClear10Ch
Physical request filter highPhysicalRequestFilterHiSet110h
PhysicalRequestFilterHiClear114h
Physical request filter lowPhysicalRequestFilterLoSet118h
PhysicalRequestFilterLoClear11Ch
Physical upper boundPhysicalUpperBound120h
Reserved124h-17Ch
Asynchronous Request Transmit
(ATRQ)		Asynchronous context controlContextControlSet180h
ContextControlClear184h
Reserved188h
Asynchronous context command pointerCommandPtr18Ch
Reserved190h-19Ch
Asynchronous Response Transmit
(ATRS)		Asynchronous context controlContextControlSet1A0h
ContextControlClear1A4h
Reserved1A8h
Asynchronous context command pointerCommandPtr1ACh
Reserved1B0h-1BCh
Asynchronous Request Receive
(ARRQ)		Asynchronous context controlContextControlSet1C0h
ContextControlClear1C4h
Reserved1C8h
Asynchronous context command pointerCommandPtr1CCh
Reserved1D0h-1DCh
Asynchronous Response Receive
(ARRS)		Asynchronous context controlContextControlSet1E0h
ContextControlClear1E4h
Reserved1E8h
Asynchronous context command pointerCommandPtr1ECh
Reserved1F0h-1FCh
Isochronous Transmit
Context n
n = 0, 1, 2, 3, ..., 7		Isochronous transmit context controlContextControlSet200h + 16*n
ContextControlClear204h + 16*n
Reserved208h + 16*n
Isochronous transmit context command pointerCommandPtr20Ch + 16*n
Reserved210h-3FCh
Isochronous Receive
Context n
n = 0, 1, 2, 3		Isochronous receive context controlContextControlSet400h + 32*n
ContextControlClear404h + 32*n
Reserved408h + 32*n
Isochronous receive context command pointerCommandPtr40Ch + 32*n
Isochronous receive context matchContextMatch410h + 32*n