ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
If the EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is 0, Cheetah- Express shall use side-band signals from the 1394b OHCI core to determine how much data to fetch when handling delayed read transactions. In this case, the cache line size register will have no effect on the design and will essentially be a read/write scratchpad register. If the EN_CACHE_LINE_CHECK bit is 1, the cache line size register is used by the bridge to determine how much data to prefetch when handling delayed read transactions. In this case, the value in this register must be programmed to a power of 2, and any value greater than 32 DWORDs will be treated as 32 DWORDs.
PCI register offset: | 0Ch | |
Register type: | Read/Write | |
Default value: | 00h |
BIT NUMBER | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESET STATE | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |