ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
As a bus master, the 1394 OHCI function supports the memory commands specified in Table 10-8. The commands include memory read, memory read line, memory read multiple, memory write, and memory write and invalidate.
The read command usage for read transactions of greater than two data phases are determined by the selection in bits 9:8 (MR_ENHANCE field) of the PCI miscellaneous configuration register at offset F0h (see Section 10.6.4.21). For read transactions of one or two data phases, a memory read command is used.
The write command usage is determined by the MWI_ENB bit 4 of the command configuration register at offset 04h (see Section 10.6.1.3). If bit 4 is asserted and a memory write starts on a cache boundary with a length greater than one cache line, memory write and invalidate commands are used. Otherwise, memory write commands are used.
PCI | COMMAND C/ BE3C/ BE0 | OHCI MASTER FUNCTION |
---|---|---|
Memory read | 0110 | DMA read from memory |
Memory write | 0111 | DMA write to memory |
Memory read multiple | 1100 | DMA read from memory |
Memory read line | 1110 | DMA read from memory |
Memory write and invalidate | 1111 | DMA write to memory |