ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
The TSB82AF15-EP requires an external reference clock for the PCI-Express interface. This section provides information concerning the requirements for this reference clock. The TSB82AF15-EP is designed to meet all stated specifications when the reference clock input is within all PCI Express operating parameters. This includes both standard clock oscillator sources or spread spectrum clock oscillator sources.
The TSB82AF15-EP supports the 100-MHz common differential reference clock. The 125-Mhz single ended option is not supported.
A single clock source with multiple differential clock outputs is connected to all PCI Express devices in the system. The differential connection between the clock source and each PCI Express device is point-to-point. This system implementation is referred to as a common clock design.
The TSB82AF15-EP is optimized for this type of system clock design. The REFCLK+ and REFCLK– pins provide differential reference clock inputs to the TSB82AF15-EP. The circuit board routing rules associated with the 100-MHz differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules itemized in 2.5-Gb/s Transmit and Receive Links. The only difference is that the differential reference clock does not require series capacitors. The requirement is a DC connection from the clock driver output to the TSB82AF15-EP receiver input.
Terminating the differential clock signal is circuit board design specific. But, the TSB82AF15-EP design does not have internal 100Ω differential or 50Ω to ground termination resistors. Both REFCLK inputs are high impedance inputs with approximately 20kΩ to ground.