ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
The 1394b OHCI function is completely reset by the internal power-on reset feature, GRST input, or PERST input. This includes all EEPROM loadable bits, power-management functions, and all remaining configuration register bits and logic.
A PCIe training control hot reset or the PCI bus configuration register reset bit (SRST) excludes the EEPROM loadable bits, power-management functions, and 1394 PHY. All remaining configuration registers and logic are reset.
If the OHCI controller is in the power-management D2 or D3 state, or if the OHCI configuration register reset bit (SoftReset) is set, the OHCI controller DMA logic and link logic is reset.
Finally, if the OHCI configuration register PHY reset bit (ISBR) is set, the 1394 PHY logic is reset.