ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
The bridge supports the transfer of data errors in both directions.
If a downstream PCIe transaction with a data payload is received that targets the internal PCI bus and the EP bit is set indicating poisoned data, the bridge must ensure that this information is transferred to the PCI bus. To do this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit calculated for each double word of data.
If the bridge is the target of a PCI transaction that is forwarded to the PCIe interface and a data parity error is detected, this information is passed to the PCIe interface. To do this, the bridge sets the EP bit in the upstream PCIe header.