SPRUJ69 December   2022 TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Inputs
    2. 2.2 Power Input [J7_CP] with LED for Status [LD2_CP][LD3_CP]
      1. 2.2.1 Power Control [SW2_CP] with LED for Status [LD5_CP] [LD6_CP] [LD7_CP]
      2. 2.2.2 Power Budget Considerations
    3. 2.3 User Inputs
      1. 2.3.1 Board Configuration Settings [SW3_CP] [SW13_CP] [SW3_SOM]
      2. 2.3.2 Boot Configuration Settings [SW9_CP] [SW8_CP]
      3. 2.3.3 Reset Pushbuttons [SW7_CP] [SW6_CP] [SW5_CP] [SW4_CP]
      4. 2.3.4 User Pushbuttons [SW2] [SW11] [SW10] [SW1] [SW12] with User LED Indication [LD9] [LD8]
    4. 2.4 Standard Interfaces
      1. 2.4.1 Uart-Over-USB [J43_CP] [J44_CP] with LED for Status [LD10_CP] [LD11_CP]
      2. 2.4.2 Gigabit Ethernet [J35_CP] with Integrated LEDs for Status
      3. 2.4.3 USB3.1 Gen1 Interface [J5_CP]
      4. 2.4.4 USB2.0 Interface [J6_CP]
      5. 2.4.5 PCIe Card Slot [J8_CP]
      6. 2.4.6 Display Port Interfaces [J36_CP] [J37_CP]
      7. 2.4.7 MicroSD Card Cage [J49_CP]
      8. 2.4.8 Stereo Audio Interface [LINE-IN J38_CP, LINE-OUT J41B_CP, J40B_CP]
    5. 2.5 Expansion Interfaces
      1. 2.5.1 Heatsink [ACC3_SOM] with Fan Header [J15_CP]
      2. 2.5.2 CAN-FD Connectors
      3. 2.5.3 Camera Interfaces [J52_CP]
      4. 2.5.4 Automation and Control Connector [J50_CP]
      5. 2.5.5 ADC [J23_CP]
      6. 2.5.6 CSI-TX [J10_SOM]
      7. 2.5.7 Accessory Power Connector [J42_CP]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
      1. 3.4.1 Power Monitoring
      2. 3.4.2 Shared Interfaces / Signal Muxing
      3. 3.4.3 Power Delivery Network (PDN)
      4. 3.4.4 Identification EEPROM
  5. 4Revision History

1.2 Key Features

Below are the EVM’s key features

  • Processor:
    • Texas Instruments Jacinto J721S2 Super-Set Processor
  • Optimized Power Management Solution:
    • Dynamic Voltage Scaling
    • Multiple Clock and Power Domains
    • Integrated Power Measurement
  • Memory:
    • 16GB LPDDR4 (4266 MT/s), support inline ECC
    • Two 512Mb Non-Volatile NOR Memories, 1x Octal-SPI and 1x Quad-SPI
    • 1Gb Non-Volatile NAND Memory, Octal-SPI
    • 16GB Non-Volatile eMMC Memory, JEDEC/MMC v5.1 compliant
    • MicroSD Card Cage Multimedia Card (MMC)/Secure Digital Card (Micro SD) Cage, UHS‐1
    • I2C EEPROM, 1Mbit
  • USB
    • USB3.1 (Gen 1) Type C Interface, support DFP, DRP, UFP modes
    • USB2.0 Hub to 2x Type A (Host), 1x Pin Header for PCIe WiFi support
    • Two USB2.0 Micro B (for Dual/Quad UART-over-USB Transceiver)
  • Display
    • VESA Display Port (v1.4), supports 4K UHD with MST support
    • VESA Display Port (v1.4), supports 2K QHD
    • Custom CSI2-TX Expansion Interface
  • Wired Network
    • Gigabit Ethernet (RJ45 Connector)
    • 5 CAN Interfaces, full CAN‐FD support
  • Camera Interfaces
    • Two CSI2-RX Camera Interfaces (Custom Interface/Dual-QSH connectors)
    • One CSI2-Tx Interface
  • Audio
    • 3.5-mm Stereo Input/Output
  • Expansion/Add-on
    • One PCIe/Gen3 4L Card Slot (with 1Lane support)
    • Multiple Pin Headers for ADC, I2C, I3C, and SPI Access
    • Expansion module(s) provide additional Ethernet, CAN, and LIN interface support
  • User Control
    • Pushbuttons (Resets, Power Modes, User Defined)
    • LEDs (Power, User Defined, Serial Port)
    • User Configurations (Boot Mode, USB Mode)
    • External or On-board Emulator Support (MIPI-60 w/ adapters to 14-pin or 20-pin CTI
  • REACH and RoHS Compliant