SLUUDA0 April 2026 BQ27Z855
The device has five main hardware-based protections—AOCD, AOCC, ASCD, ACUV, and ACOV—with adjustable thresholds and delay times. For current-based protections (AOCD, AOCC, ASCD), the Threshold settings are in mV; therefore, the actual current that triggers the protection is based on the RSENSE used in the schematic design. For voltage-based protections (ACUV, ACOV), the thresholds are configured in mV.
For details on how to configure the AFE hardware protection, refer to the registers in the AFE section.
All of the hardware-based protections provide a Trip/Latch Alert/Recovery protection. The latch feature stops the FETs from toggling on and off continuously on a persistent faulty condition.
In general, when a fault is detected after the Delay time, the CHG and DSG FETs will be disabled (Trip stage), and an internal fault counter will be incremented (Alert stage). Since both FETs are off, the current will drop to 0 mA. After Recovery time, the CHG and DSG FETs will be turned on again (Recovery stage).
If the alert is caused by a current spike, the fault count will be decremented after Counter Dec Delay time. If this is a persistent faulty condition, the device will enter the Trip stage after Delay time, and repeat the Trip/Latch Alert/Recovery cycle. The internal fault counter is incremented every time the device goes through the Trip/Latch Alert/Recovery cycle. Once the internal fault counter hits the Latch Limit, the protection enters a Latch stage and the fault will only be cleared through the Latch Reset condition.
The Trip/Latch Alert/Recovery/Latch stages are documented in each of the following hardware-based protection sections.
The device uses embedded pack configuration ([NR] = 1). The latch reset condition is based on the Reset time parameter.