SLUUDA0 April 2026 BQ27Z855
The CHGR_DET bit is a status indicator reflecting whether a valid upstream charger is attached. The device firmware monitors the voltage difference between PACK+ (VPACK) and the battery (VBAT) using configurable thresholds with hysteresis to prevent noise-induced toggling.
Entry Condition (CHGR_DET = 1): When (VPACK - VBAT) >= CHGR_DET On Voltage (default 150 mV), the CHGR_DET bit sets, indicating a valid charger is attached.
Exit Condition (CHGR_DET = 0): When (VBAT - VPACK) >= CHGR_DET Off Voltage (default 10 mV), the CHGR_DET bit clears, indicating the charger is removed or invalid.
The separate On and Off voltage thresholds create a hysteresis window that prevents rapid toggling of the CHGR_DET, LIN, and ID status bits due to measurement noise. This is particularly important during Ideal Diode mode with no charger attached or during supplement mode transitions where PACK voltage may briefly drop below BAT voltage.
The CHGR_DET status serves as a primary input to the CHG FET finite state machine and the linear charge profile state machine, enabling immediate transition into Linear mode to initiate battery charging upon detection (provided the linear charger is enabled and no protections are active), while forcing exit to Ideal Diode or OFF states when the charger is removed.
Example with default settings (On = 0 mV, Off = 10 mV):
The charger detection thresholds are configured via the following Data Flash parameters in Advanced Charge Algorithm > Charger:
| Parameter | Default | Unit | Description |
|---|---|---|---|
| CHGR_DET On Voltage | 150 | mV | Threshold to enter CHGR_DET state (NEW) |
| CHGR_DET Off Voltage | 10 | mV | Threshold to exit CHGR_DET state (renamed from Vacp Hysteresis) |
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Advanced Charge Algorithm | Charger | CHGR_DET On Voltage | I2 | -32768 | 32767 | 0 | mV |
Description: This parameter sets the voltage threshold for entering the CHGR_DET state. When the voltage difference (VPACK - VBAT) is greater than or equal to this threshold, the CHGR_DET bit in ChargerStatus() will be set to 1, indicating that an upstream charger is detected.
Entry Condition: CHGR_DET = 1 when (VPACK - VBAT) >= CHGR_DET On Voltage
Default Value: 0 mV. With the default setting, CHGR_DET will set as soon as VPACK >= VBAT.
Configuration Notes: Increasing this value requires a larger voltage difference before charger detection occurs. This can be useful in applications where a voltage margin is needed before activating the linear charger.
| Class | Subclass | Name | Type | Min | Max | Default | Unit |
|---|---|---|---|---|---|---|---|
| Advanced Charge Algorithm | Charger | CHGR_DET Off Voltage | I2 | -32768 | 32767 | 10 | mV |
Description: This parameter sets the voltage threshold for exiting the CHGR_DET state. When the voltage difference (VBAT - VPACK) is greater than or equal to this threshold, the CHGR_DET bit in ChargerStatus() will be cleared to 0, indicating that the upstream charger is no longer detected.
Exit Condition: CHGR_DET = 0 when (VBAT - VPACK) >= CHGR_DET Off Voltage
Equivalent: CHGR_DET = 0 when VPACK <= VBAT - CHGR_DET Off Voltage
Default Value: 10 mV. This provides a 10 mV hysteresis band to prevent noise-induced toggling.
Configuration Notes: This parameter was previously named Vacp Hysteresis with a default of 0 mV. The renamed parameter with 10 mV default provides improved noise immunity.
Parameter Renamed: In firmware version v0.03 (BMSFW-11389), the parameter Charger Vacp Hysteresis was renamed to Charger CHGR_DET Off Voltage and the default value was changed from 0 mV to 10 mV.
The combination of CHGR_DET On Voltage and CHGR_DET Off Voltage creates a hysteresis window that provides stable charger detection even in the presence of voltage measurement noise.
Benefit: This hysteresis prevents rapid toggling of the CHGR_DET, LIN, and ID status bits when VPACK is approximately equal to VBAT, which commonly occurs during:
The CHGR_DET detection interacts with the following status bits and configuration parameters:
| Parameter/Status | Location | Description |
|---|---|---|
| SBS:ManufacturerAccess(0x00B5)[CHGR_DET] | Bit 1 | Reflects the current charger detection state. Automatically controlled by firmware in automatic mode (Advanced Charge Algorithm: Charger: Configuration[PAR_PACK]=0). Host-writable in parallel pack mode (Advanced Charge Algorithm: Charger: Configuration[PAR_PACK]=1) |
| SBS:ManufacturerAccess(0x00B5)[LIN] | Bit 2 | Linear mode active. Requires [CHGR_DET] = 1 and [LINCHGR] = 1 |
| SBS:ManufacturerAccess(0x00B5)[ID] | Bit 3 | Ideal Diode mode active. Typically active when [CHGR_DET] = 0 |
| SBS:ManufacturerAccess(0x00B5)[LINCHGR] | Bit 0 | Reflects if linear charger is enabled in configuration |
| Advanced Charge Algorithm: Charger: Configuration[LINCHGR] | Settings: Configuration | Must be enabled (=1) for linear charger functionality |
| Advanced Charge Algorithm: Charger: Configuration[PAR_PACK] | Settings: Configuration | When enabled (=1), disables automatic [CHGR_DET] detection and enables host control via SBS:ManufacturerAccess(0x00B5) writes. See Parallel Pack (PAR_PACK) Mode section |
When the Advanced Charge Algorithm: Charger: Configuration[PAR_PACK] configuration bit is enabled (set to 1), the CHGR_DET functionality transitions from automatic voltage-based detection to host-controlled mode. This mode is designed for applications using parallel pack configurations where hardware-based charger detection may not be reliable or where the host system requires direct control over charger detection state.
Behavior Change:
Host Control via SBS:ManufacturerAccess(0x00B5): In parallel pack mode, the host writes the desired [CHGR_DET] state by sending a command. The command includes the data byte, checksum, and length fields.
// MAC 0x00B5 Commands for CHGR_DET control in parallel pack mode
// Enable CHGR_DET (set bit 1):
B5 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 48 06
// Byte 0-1: B5 00 (MAC address)
// Byte 2: 02 (data byte with CHGR_DET bit 1 set)
// Bytes 3-33: 00 (padding)
// Byte 34: 48 (I2C checksum)
// Byte 35: 06 (command length)
// Disable CHGR_DET (clear bit 1):
B5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4a 06
// Byte 0-1: B5 00 (MAC address)
// Byte 2: 00 (data byte with CHGR_DET bit 1 clear)
// Bytes 3-33: 00 (padding)
// Byte 34: 4a (I2C checksum)
// Byte 35: 06 (command length)
Only the [CHGR_DET] bit (Bit 1) is writable in parallel pack mode via SBS:ManufacturerAccess(0x00B5) command. All other bits in SBS:ChargerStatus(0x00B5) remain read-only and reflect firmware-determined states ([LIN], [ID], [LINCHGR]). The I2C checksum and length fields must be included in the command for proper delivery.
Use Cases: Parallel pack mode is essential for applications with multiple battery packs in parallel, such as:
Interaction with Other Features: Even in parallel pack mode, the automatic charging state machine (LIN/ID transition logic) operates normally based on the host-written [CHGR_DET] state: