ZHCSS38 july 2020 TSB82AF15-EP
PRODUCTION DATA
There are five TSB82AF15-EP reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets that are controlled by sending a PCIe hot reset or setting a configuration register bit. Table 10-1 identifies these reset sources and describes how the TSB82AF15-EP responds to each reset.
RESET OPTION | TSB82AF15-EP FEATURE | RESET RESPONSE |
---|---|---|
TSB82AF15-EP internally-generated power-on reset | During a power-on cycle, the TSB82AF15-EP asserts an internal reset and monitors VDD_15_COMB. When this supply reaches 90% of the nominal input voltage specification, power is considered stable. After stable power, the TSB82AF15-EP monitors the PCIe reference clock (REFCLK) and waits 10 μs after active clocks are detected. Then, internal power-on reset is deasserted. | When the internal power-on reset is asserted, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. In addition, the TSB82AF15-EP asserts the internal PCI bus reset. |
Global reset input ( GRST, ) | When GRST is asserted low, an internal power-on reset occurs. This reset is asynchronous. | When GRST is asserted low, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. When the rising edge of GRST occurs, the bridge samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The bridge starts link training within 80 ms after GRST is deasserted. |
PCIe reset input ( PERST, ) | This TSB82AF15-EP input terminal is used by an upstream PCIe device to generate a PCIe reset and to signal a system power good condition. | When PERST is asserted low, all control register bits that are not sticky are reset. Within the configuration register maps, the sticky bits are indicated by the symbol. Also, all state machines that are not associated with sticky functionality are reset. |
When PERST is asserted low, the TSB82AF15-EP generates an internal PCIe reset as defined in the PCI Express Specification. | ||
When PERST transitions from low to high, a system power good condition is assumed by the TSB82AF15-EP. | In addition, the TSB82AF15-EP asserts the internal PCI bus reset. | |
Note: The system must assert PERST before power is removed, before REFCLK is removed or before REFCLK becomes unstable. | When the rising edge of PERST occurs, the TSB82AF15-EP samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, a download cycle is initiated. Also, the process to configure and initialize the PCIe link is started. The TSB82AF15-EP starts link training within 80 ms after PERST is deasserted. | |
PCIe training control hot reset | The TSB82AF15-EP responds to a training control hot reset received on the PCIe interface. After a training control hot reset, the PCIe interface enters the DL_DOWN state. | In the DL_DOWN state, all remaining configuration register bits and state machines are reset. All remaining bits exclude sticky bits and EEPROM loadable bits. All remaining state machines exclude sticky functionality and EEPROM functionality. |
Within the configuration register maps, the sticky bits are reset by a global reset ( GRST) or the internally-generated power-on reset and EEPROM loadable bits are rest by a PCIe reset ( PERST), GRST, or internally generated power-on reset. | ||
In addition, the TSB82AF15-EP asserts the internal PCI bus reset. | ||
PCI bus reset | System software has the ability to assert and deassert the PCI bus reset on the secondary PCI bus interface. | When bit 6 (SRST) in the TSB82AF15-EP control register at offset 3Eh (see Section 10.6.1.30) is asserted, the TSB82AF15-EP asserts the internal PCI bus reset. A 0b in the SRST bit deasserts the PCI bus reset. |