ZHCSHE0 December 2017 TMS320F28377D-EP
Figure 4-16 provides a high-level view of the interrupt architecture.
As shown in Figure 4-16, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group.