126.96.36.199.2 ADC Timing Diagrams
Table 4-49 shows the ADC timings in 12-bit mode (SYSCLK cycles). Table 4-50 shows the ADC timings in 16-bit mode. Figure 4-34 and Figure 4-35 show the ADC conversion timings for two SOCs given the following assumptions:
- SOC0 and SOC1 are configured to use the same trigger.
- No other SOCs are converting or pending when the trigger occurs.
- The round robin pointer is in a state that causes SOC0 to convert first.
- ADCINTSEL is configured to set an ADCINT flag upon end of conversion for SOC0 (whether this flag propagates through to the CPU to cause an interrupt is determined by the configurations in the PIE module).
The following parameters are identified in the timing diagrams:
- The parameter tSH is the duration of the S+H window. At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH will not necessarily be the same for different SOCs.
- The parameter tLAT is the time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register. If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
- The parameter tEOC is the time from the end of the S+H window until the next ADC conversion S+H window can begin. In 16-bit mode, this will coincide with the latching of the conversion results, while in 12-bit mode, the subsequent sample can start before the conversion results are latched.
- The parameter tINT is the time from the end of the S+H window until an ADCINT flag is set (if configured). If the INTPULSEPOS bit in the ADCCTL1 register is set, this will coincide with the conversion results being latched into the result register. If the bit is cleared, this will coincide with the end of the S+H window.