ZHCSHE0 December 2017 TMS320F28377D-EP
Table 4-7 shows the frequency requirements for the input clocks. Table 4-16 shows the crystal equivalent series resistance requirements. Table 4-8 shows the X1 input level characteristics when using an external clock source. Table 4-9 and Table 4-10 show the timing requirements for the input clocks. Table 4-11 shows the PLL lock times for the Main PLL and the USB PLL.